What's Changed

• [LLHD] Use initial signal value to fill gaps in CombineDrives by @fabianschuiki in #8636
• Datapath Dialect Definition by @cowardsa in #8638
• [RTG] Add ValidationTypeInterface by @maerhart in #8639
• [Python] Add Python bindings for AIG dialect by @uenoku in #8646
• [circt-verilog] Add MapArithToComb pass to pipeline by @fabianschuiki in #8649
• [ExportVerilog] Add support for hw.array_inject by @fabianschuiki in #8645
• [AIG] Enhance longest path analysis with detailed timing statistics and JSON output by @uenoku in #8644
• [AIG][NFC] Introduce a helper struct to manage result paths by @uenoku in #8651
• [AIG][CAPI] Add C API for LongestPathAnalysis by @uenoku in #8652
• [RTG] Add EmbedValidationValuesPass by @maerhart in #8648
• [PyCDE] Improve location information by @teqdruid in #8635
• [Datapath] Operator definitions and canonicalization patterns by @cowardsa in #8647
• [ESI] Make RAM delarations' addresses unsigned by @teqdruid in #8658
• [PyCDE] Add bundle transform and rework coerce by @teqdruid in #8660
• [LLHD] Add loop unrolling pass by @fabianschuiki in #8620
• [seq] Simplify clock enabled when constant enabled. by @jpienaar in #8655
• [circt-synth] Add -emit-bytecode option by @uenoku in #8661
• [LLHD] Make Deseq pass emit seq.firreg instead of seq.compreg by @fabianschuiki in #8662
• [importverilog] Lvalue RangelSelect and ElementSelect to use range. by @jpienaar in #8663
• Convert to CF before running LLHD inline. by @jpienaar in #8667
• [FIRRTL] Delete BlackBoxResourceFileNameAnno by @seldridge in #8669
• [RTG] Add LowerValidateToLabels pass by @maerhart in #8666
• [AIG][Python] Add Python bindings for LongestPathAnalysis by @uenoku in #8659
• [FIRRTL] Lint XMRs in the "design" by @seldridge in #8668
• [ImportVerilog] Add support for SVA declarations by @towoe in #8656
• [Datapath] Conversion Pass Comb to Datapath by @cowardsa in #8664
• Add SitestBlackBoxLibrariesAnnotation; process in CreateSiFiveMetadataPass by @tmckay-sifive in #8670
• [FIRRTL] Fix inject-dut-hier deleting new top by @seldridge in #8678
• [ImportVerilog] Incorporate block names to variable/instance names by @fabianschuiki in #8680
• [RTG] Add Randomization Pipeline by @maerhart in #8675
• Insert probes at least post def. by @jpienaar in #8674
• [FIRRTL] Lower registers under ifdefs by @rwy7 in #8605
• [MooreToCore] Lower exponentiation to math.ipowi (PowUOpConversion) by @liamslj13 in #8654
• [circt-synth] [Synthesis] Add synthesis pipeline and refactor the lib structure by @uenoku in #8681
• [Comb] Replace mux cond uses in true/false operand with constant by @fabianschuiki in #8685
• [FIRRTL][firtool] Enable advanced layer sink by default by @rwy7 in #8683

New Contributors

• @tmckay-sifive made their first contribution in #8670

Full Changelog: firtool-1.124.0...firtool-1.125.0