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[ImportVerilog] Add support for SVA declarations #8656

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Merged
merged 2 commits into from
Jul 9, 2025
Merged

[ImportVerilog] Add support for SVA declarations #8656

merged 2 commits into from
Jul 9, 2025

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towoe
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@towoe towoe commented Jul 7, 2025

Support 'sequence' and 'property' declarations.
Slang already handles the references and variable ports. Make visiting of 'AssertionInstance' legal.
Those are part of 'Expressions' of the 'Simple' case. Adapt the visitor to handle the different return types.

@towoe
[ImportVerilog] Add support for SVA declarations
39d7300 
Support 'sequence' and 'property' declarations.
Slang already handles the references and variable ports. Make visiting
of 'AssertionInstance' legal.
Those are part of 'Expressions' of the 'Simple' case. Adapt this visitor
to handle the varied return types.
@towoe
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towoe commented Jul 7, 2025

One benefit of supporting the symbols would be that the named properties are then inlined.
If there is a proper path back to SV, this could provide a way to convert the named properties for other tools, e.g. Verilator.

fabianschuiki
fabianschuiki approved these changes Jul 8, 2025
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🥳 This is really cool! Great idea to just inline the sequence/property definitions for now. We can always come back later and think about how you would define and reuse sequences/properties in the IR. Love this! 🥳

@towoe @fabianschuiki
Check for multiple types
b9adf98 
Co-authored-by: Fabian Schuiki <fabian@schuiki.ch>
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towoe commented Jul 9, 2025

Thanks for the feedback @fabianschuiki!
Yeah, doing more optimization in the IR could be quite useful. Hopefully that is not too much technical debt to get to later :)
If you could push it, that would be great. Thanks!

@fabianschuiki fabianschuiki merged commit f91e77c into llvm:main Jul 9, 2025
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@towoe @fabianschuiki