Use the names of surrounding generate blocks as a prefix for variable
and instance names. This makes the names match up more closely with how
existing EDA tools would label variables and instances embededded in
generate blocks.

Consider the following Verilog input:

```systemverilog
module Top;
  int x;
  begin : foo
    int y;
    for (genvar i = 2; i < 6; ++i) begin : bar
      int z;
    end
  end
endmodule
```

The ImportVerilog conversion pass will now produce the following
variables:

```mlir
%x = moore.variable : <i32>            // before: %x
%foo.y = moore.variable : <i32>        // before: %y
%foo.bar_2.z = moore.variable : <i32>  // before: %z
%foo.bar_3.z = moore.variable : <i32>  // before: %z_0
%foo.bar_4.z = moore.variable : <i32>  // before: %z_1
%foo.bar_5.z = moore.variable : <i32>  // before: %z_2
```

This closely matches names like `foo.bar[2].z` or `foo_bar_2_z` that
would be generated by common EDA tools. Ideally we would be able to use
a name like `foo.bar[2].z` directly, but ExportVerilog currently does
not support escaped identifiers, causing the name to be sanitized to
something like `foo_bar5B25D_z`.

By incorporating for-generate loop indices and block names into the
variable name, logical equivalence checking should become easier and the
signal names in Arcilator waveforms will match user expectations more
closely.

Fixes #8679.