[ESI] Make RAM delarations' addresses unsigned #8658
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Using signless ints as the address was just wrong. It was probably done to avoid incomplete lowerings, which have been addressed.
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Pull Request Overview
This PR changes RAM declaration addresses to use unsigned integer types throughout the ESI dialect and its tests, updating both the code generator and expected outputs.
- Switch address ports to unsigned (
uiN) in MLIR tests and service definitions. - Update C++ service port generation and SystemVerilog memory instantiation to use unsigned address types, inserting bitcasts to signless for indexing.
- Adjust PyCDE front end and software integration tests to use
UInt/plain integer writes.
Reviewed Changes
Copilot reviewed 8 out of 8 changed files in this pull request and generated 3 comments.
Show a summary per file
| File | Description |
|---|---|
| test/Dialect/Handshake/lower-extmem-esi.mlir | Updated expected esi.service.req bundles to ui4. |
| test/Dialect/ESI/services.mlir | Switched memory service port labels from i5 to ui5. |
| lib/Dialect/ESI/ESIStdServices.cpp | Generate address IntegerType as unsigned. |
| lib/Dialect/ESI/ESIServices.cpp | Insert hw.bitcast from unsigned to signless before indexing. |
| integration_test/Dialect/ESI/runtime/loopback.mlir | Change RAM address field in struct to ui5. |
| frontends/PyCDE/test/test_esi.py | Update CHECK patterns to expect ui in struct fields. |
| frontends/PyCDE/src/pycde/esi.py | Change address_type from Bits to UInt. |
| frontends/PyCDE/integration_test/test_software/esi_ram.py | Write raw integers instead of single-element lists. |
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Using signless ints as the address was just wrong. It was probably done to avoid incomplete lowerings, which have been addressed.