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@seldridge seldridge released this 02 Jul 20:38
· 278 commits to main since this release
firtool-1.124.0
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seldridge Schuyler Eldridge
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Learn about vigilant mode.
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Learn about vigilant mode.

What's Changed

  • [Support] Add concatPath method to InstancePathCache by @uenoku in #8627
  • [RTG] Add CAPI and python bindings to register passes by @maerhart in #8632
  • [MooreToCore] Lower exponentiation to math.ipowi (PowSOpConversion) by @liamslj13 in #8574
  • [ImportVerilog] Detect and fixup two-state-exhaustive case statements by @fabianschuiki in #8628
  • [LLHD] Remove drive-only signals in Sig2Reg pass by @fabianschuiki in #8629
  • [AIG] Refactor Longest Path Analysis with hierarchical path support by @uenoku in #8630
  • [RTG] Add validate operation by @maerhart in #8631
  • [RTG] Add UniqueValidateOpsPass by @maerhart in #8633
  • [AIG] Fix history's instance path update in LongestPathAnalysis by @uenoku in #8637
  • [FIRRTL] Allow layers to RWProbe into the design by @rwy7 in #8641
  • [circt-bmc] Support registers with reset signals by @liuyic00 in #8622

New Contributors

Full Changelog: firtool-1.123.2...firtool-1.124.0

Contributors

fabianschuiki, rwy7, and 4 other contributors
Assets 20
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