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[FIRRTL] Allow layers to RWProbe into the design #8641
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LGTM
// CHECK: %w = firrtl.wire sym @sym : !firrtl.uint<1> | ||
// CHECK-NEXT: firrtl.layerblock @A { | ||
// CHECK-NEXT: %0 = firrtl.ref.rwprobe <@SinkRWProbe::@sym> : !firrtl.rwprobe<uint<1>> | ||
// CHECK-NEXT: %1 = firrtl.ref.cast %0 : (!firrtl.rwprobe<uint<1>>) -> !firrtl.rwprobe<uint<1>, @A> | ||
// CHECK-NEXT: firrtl.ref.define %p, %1 : !firrtl.rwprobe<uint<1>, @A> | ||
// CHECK-NEXT: } |
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Not for this PR: it seems like not sinking %w
is a missed optimization here given that the only user of the wire is (now) inside the layer block. This is probably worth looking into in a follow-on.
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Agreed. It's the symbol from the rwprobe preventing advanced-layer-sink from sinking the op. Maybe we can revisit the use of symbols for rwprobes, or teach ALS how to find and interpret inner symbol users.
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Forceable would help with this, if we aren't removing it (it's presently unused, see #7138 which removes it).
An old verifier for the RWPRobe op asserted that the target was under at least the same conditions as the probe op itself, ensuring that we could not create a forceable probe from within a layer, to something outside of that layer. This verifier helped ensure that "enabling a layer cannot change the behaviour of the design". We no longer have nor want this restriction, so this PR is removing the verifier.
This fixes an issue with advanced layer sink, where ALS will sink rwprobe ops into a layer and trigger this verification check.
Fixes: #8640