One of the new features of GHDL (which I am most excited about) is the "implicit standard version downgrade" that is achieved with ghdl --synth. I.e., we can take any modern and complex VHDL codebase with 2008 features and GHDL will provide a plain old 1993 netlist. Vendor tools with poor VHDL support will probably choke on 2008 sources but they will gracefully accept the 1993 netlist.

However, in essence, the VHDL netlist generated by ghdl --synth is equivalent to Yosys' C API (which is used by ghdlsynth-beta). Hence, there are currently two synthesis generators/elaborators/backends. Some other tools in the EDA industry might benefit from additional output formats. This issue is to gather ideas and discuss such other formats:

Verilog

I believe it is already possible to generate Verilog from Yosys' output. However, Yosys' does not only do synthesis, but also technology mapping.

• Would it make sense to generate some Verilog sources which are equivalent to Yosys' input instead of the output?
• What's the use case for desiring synthesised but not technology mapped Verilog sources? The use case for VHDL is poor language support.
• Is it worth creating en explicit backend instead of using some external tool to convert the current output (VHDL netlist)?
• Would this make it easier to merge VHDL and Verilog sources through components/black boxes?

EDIF

AFAIK, there is no "standard" EDIF. I think it would be great to generate an EDIF which is generic enough to be accepted by any open source or vendor tool. But maybe that's not possible and GHDL would need to generate flavours of EDIF. See https://j.mp/openfpga-diagram. OTOH, the generation of EDIF flavours from a single source is a feature that can be externalised (to be shared with other FOSS projects).

Ref #957, #908