The tool I am using must not have VHDL-2008 standard as the top level entity. The documentation of GHDL states that

The 93, 93c, 00 and 02 standards are considered compatible: you can elaborate a design mixing these standards. However, 87, 93 and 08 are not compatible.

So 93 is compatible with 93c, 00 and 02 but incompatible with 87 and 08.
87 is not compatible with 93 and 08.

This is clear but is 87 compatible with the rest? Same for 08. I only need the non-2008 for the wrapper the rest of the design is VHDL-2008.

Another question: Is there any way to link Verilog sources with VHDL? I found a discussion about this for iVerilog, which appearently has limited VHDL support and development on VHDL support has been abandoned (never used iVerilog I am not too well informed).