📦 Tool to enable package managing for HDL VIP or IP cores (Verilog, SystemVerilog, VHDL) using Python pip
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Updated
Jan 26, 2024 - Python
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ip-core
Here are 5 public repositories matching this topic...
A Python-based IP Core Management Infrastructure.
infrastructure database simulation vhdl intel python3 xilinx synthesis altera modelsim questasim xilinx-vivado quartus-prime vhdl-verification ip-core riviera-pro
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Apr 29, 2021 - Python
Configurable, high-performance FFT hardware IP core for ASIC/FPGA. Pipelined radix-2 DIF, 256–4096-point support, 16-bit fixed-point, double-buffered memory, APB/AXI interfaces. Optimized for throughput and low latency.
asic fpga pipeline signal-processing rad verilog digital-signal-processing apb ip-core hardware-ip vyges vyges-ip ix-2
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Aug 1, 2025 - Python
🧩 Starter template for ASIC hardware IP blocks with Vyges metadata, OpenLane integration, and comprehensive documentation
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Updated
Aug 1, 2025 - Python
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