Consider this Verilog snippet:

module Top;
  int x;
  begin : foo
    int y;
    for (genvar i = 0; i < 4; ++i) begin : bar
      int z;
    end
  end
endmodule

In most EDA tools this would generate the following signals:

Top/x
Top/foo.y
Top/foo.bar[0].z
Top/foo.bar[1].z
Top/foo.bar[2].z
Top/foo.bar[3].z

We should do the same thing. ImportVerilog currently ignores block names, thus creating the following signals:

Top/x
Top/y
Top/z
Top/z_0
Top/z_1
Top/z_2

When picking names for signals and instances, try to incorporate the enclosing block names.