This came up when looking into using firrtl.transforms.BlackBoxTargetDirAnno after #8669 was merged. Unfortunately I couldn't figure out a minimal example to recreate this issue. I'm attaching a Rocket Chip design generated from a Chipyard fork which is using Chisel 7.0.0-RC2 and firtool-1.124.0. When I add the following annotation to the design:

  {
    "class":"firrtl.transforms.BlackBoxTargetDirAnno",
    "targetDir":"black-boxes"
  }

I would expect all of the black box files to be placed in the black-boxes subdirectory inside the firtool output directory. However, when I run this command:

firtool --annotation-file=rocket.annos.json --split-verilog -o out-dir rocket.fir

I see the following:

$ cat out-dir/firrtl_black_box_resource_files.f
black-boxes/ClockSourceAtFreqMHz.v
black-boxes/EICG_wrapper.v
black-boxes/GenericDigitalInIOCell.v
black-boxes/GenericDigitalOutIOCell.v
black-boxes/SimDRAM.cc
black-boxes/SimDRAM.v
black-boxes/SimJTAG.cc
black-boxes/SimJTAG.v
black-boxes/SimTSI.cc
black-boxes/SimTSI.v
black-boxes/SimUART.cc
black-boxes/SimUART.v
black-boxes/mm.cc
black-boxes/mm_dramsim2.cc
black-boxes/remote_bitbang.cc
black-boxes/testchip_htif.cc
black-boxes/testchip_tsi.cc
black-boxes/uart.cc
plusarg_reader.v

Notably, plusarg_reader.v is placed directly in out-dir, rather than in the black-boxes subdirectory. Any ideas why this might be happening? You can recreate this by downloading the attached archive, and then running:

$ tar xf rocket-chip-black-box-path-error.tar.gz
$ cd rocket-chip-black-box-path-error/
$ ./run.sh

rocket-chip-black-box-path-error.tar.gz