fix up extra waveform dump behavior in svsim #4592
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When added require statement in ChiselSim/svsim, the delay value will be set to 0, which will cause an extra dump waveform behavior. So we only call `eval_step` once to update the design model
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When added require statement in ChiselSim/svsim, the delay value will be set to 0, which will cause an extra dump waveform behavior. So we only call `eval_step` once to update the design model (cherry picked from commit 3380196)
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When added require statement in ChiselSim/svsim, the delay value will be set to 0, which will cause an extra dump waveform behavior. So we only call `eval_step` once to update the design model (cherry picked from commit 3380196) Co-authored-by: qiming chu <cchuqiming@gmail.com>
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When added require statement in ChiselSim/svsim, the
delayvalue will be set to 0, which will cause an extra dump waveform behavior. So we only calleval_steponce to update the design model.This will fix #4516.
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docs/src?Type of Improvement
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3.6.x,5.x, or6.xdepending on impact, API modification or big change:7.0)?Enable auto-merge (squash), clean up the commit message, and label withPlease Merge.Create a merge commit.