ChiselSim: vcd shows clock=1 for threes consecutive time steps #4516
Description
Type of issue: Bug Report
Please provide the steps to reproduce the problem:
See below for complete project. I modified the simulator to export vcd and keep the temp files.
class TmpUnitTests extends AnyFlatSpec {
behavior of "Tmp"
it should "have an oscilating clock" in {
simulate(new TmpTestBench) { dut =>
dut.clock.step()
dut.io.in.valid.poke(true.B)
dut.io.in.bits.poke(42.U)
dut.io.in.ready.expect(true.B) // Remove this to fix the clock
dut.clock.step()
dut.io.out.expect(42.U)
dut.clock.step()
}
}
}
What is the current behavior?
___ _
clock: _| |_|
What is the expected behavior?
_ _ _
clock: _| |_| |_|
Please tell us about your environment:
- version: `7.0.0-M2`
- OS: `Linux calm 6.8.0-48-generic #48-Ubuntu SMP PREEMPT_DYNAMIC Fri Sep 27 14:04:52 UTC 2024 x86_64 GNU/Linux`
Other Information
This is sent to the "simulation" executable.
W 1
T 0 0,1-1*1
S 4 1
S 3 2a
R 0
G u 5
T 0 0,1-1*1
G u 2
T 0 0,1-1*1
D
I i remove line 5 (R 0), everything looks fine.
Here's the complete project:
src/test/scala/TmpTests.scala
package tmp
import chisel3._
import chisel3.util._
import org.scalatest.flatspec.AnyFlatSpec
import svsim._
import chisel3.simulator._
import java.nio.file.Files
import java.nio.file.Paths
import java.io.File
import scala.reflect.io.Directory
object Simulator extends PeekPokeAPI {
def simulate[T <: RawModule](
module: => T
)(body: (T) => Unit): Unit = {
makeSimulator
.simulate(module)({ module =>
module.controller.setTraceEnabled(true)
body(module.wrapped)
})
.result
}
import Simulator._
private class DefaultSimulator(val workspacePath: String) extends SingleBackendSimulator[verilator.Backend] {
val backend = verilator.Backend.initializeFromProcessEnvironment()
val tag = "default"
val commonCompilationSettings = CommonCompilationSettings()
val backendSpecificCompilationSettings = verilator.Backend.CompilationSettings(
traceStyle = Some(verilator.Backend.CompilationSettings.TraceStyle.Vcd(traceUnderscore = true))
)
}
private def makeSimulator: DefaultSimulator = {
val id = ProcessHandle.current().pid().toString()
val className = getClass().getName().stripSuffix("$")
new DefaultSimulator(Files.createDirectories(Paths.get(s"test_run_dir/${className}_${id}")).toString)
}
}
import Simulator._
class TmpIO extends Bundle {
val in = Flipped(Decoupled(UInt(8.W)))
val out = Output(UInt(8.W))
}
class Tmp extends Module {
val io = IO(new TmpIO)
val r = RegInit(0.U(8.W))
io.out := r
when(io.in.valid) {
r := io.in.bits
}
io.in.ready := io.in.valid
}
class TmpTestBench extends Module {
val io = IO(new TmpIO)
val dut = Module(new Tmp)
dut.io <> io
}
class TmpUnitTests extends AnyFlatSpec {
behavior of "Tmp"
it should "have an oscilating clock" in {
simulate(new TmpTestBench) { dut =>
dut.clock.step()
dut.io.in.valid.poke(true.B)
dut.io.in.bits.poke(42.U)
dut.io.in.ready.expect(true.B) // Remove this to fix the clock
dut.clock.step()
dut.io.out.expect(42.U)
dut.clock.step()
}
}
}
build.sbt
// See README.md for license details.
ThisBuild / scalaVersion := "2.13.14"
ThisBuild / version := "0.1.0"
ThisBuild / organization := "%ORGANIZATION%"
val chiselVersion = "7.0.0-M2"
lazy val root = (project in file("."))
.settings(
name := "%NAME%",
libraryDependencies ++= Seq(
"org.chipsalliance" %% "chisel" % chiselVersion,
"org.scalatest" %% "scalatest" % "3.2.16" % "test",
),
scalacOptions ++= Seq(
"-language:reflectiveCalls",
"-deprecation",
"-feature",
"-Xcheckinit",
"-Ymacro-annotations",
),
addCompilerPlugin("org.chipsalliance" % "chisel-plugin" % chiselVersion cross CrossVersion.full),
)