Skip to content

boards/nucleo-f767zi: add correct flash bank openocd config [backport 2020.01] #13219

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom
Merged
merged 2 commits into from
Jan 28, 2020
Merged

boards/nucleo-f767zi: add correct flash bank openocd config [backport 2020.01] #13219

merged 2 commits into from
Jan 28, 2020

Conversation

fjmolinas
Copy link
Contributor

Backport of #13179

Contribution description

This pr fixes flashing bin files on nucleo-f767zi, this issue is not present on all nucleo-f7* boards.

Flashing bin files on nucleo-f767zi fails for two reasons:

  • fails to probe flash
### Flashing Target ###
WARN: Failed to probe board flash.
WARN: Falling back to using the openocd configuration value.
Binfile detected, adding ROM base address: 0x00000000
Flashing with IMAGE_OFFSET: 0x00000000
  • backup openocd configuration value is wrong
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
flash bank $_CHIPNAME.otp stm32f2x 0x1ff0f000 0 0 0 $_TARGETNAME

Playing around with openocd.sh I have found that flash probe 0 fails on this BOARD when srst is asserted, but if srst is deasserted probing fails anyway if the device is hardfaulted or in sleep mode.

I couldn't find the reason why probing fails in this case, but to keep asserting srst I added the correct FLASH_ADDR in our stm32f7.cfg file and added FLASH_BANK to allow specifying which flash bank to use as configuration input and not use the one in target/stm32f7x.cfg

Testing procedure

make -C tests/riotboot/ BOARD=nucleo-f767zi flash

@fjmolinas
dist/tools/openocd/openocd.sh: add FLASH_BANK
b3b4587 
Allow specifying index of `flash bank` to read configuration from
in cases where the configuration provided in openocd is incorrect.

This is the case for the majority of stm32 boards where it relies
on `flash probe` to get the correct value.

(cherry picked from commit 53f60db)
@fjmolinas
boards/common/stm32f7: add correct flash bank configuration
f1cf580 
openocd configuration file for `stm32f7` relies on probing to find out
FLASH_ADDR. On nucleo-f767zi board probing (`flash probe 0`) fails when
`srst` is asserted, but `srst` needs to be asserted to be able to flash
the `BOARD` when sleeping or after a hardfault.

To circumvent this in boards/common/stm32/dist/stm32f7.cfg we define a new
flash bank with the appropriate fash start address and specify that this is
the flash bank to be used as default configuration instead of the
default by setting FLASH_BANK=4

(cherry picked from commit 1dec5ba)
@fjmolinas fjmolinas added CI: ready for build If set, CI server will compile all applications for all available boards for the labeled PR Process: release backport Integration Process: The PR is a release backport of a change previously provided to master Type: bug The issue reports a bug / The PR fixes a bug (including spelling errors) labels Jan 28, 2020
@fjmolinas fjmolinas requested a review from aabadie January 28, 2020 09:53
@fjmolinas fjmolinas mentioned this pull request Jan 28, 2020
Merged
aabadie
aabadie approved these changes Jan 28, 2020
View reviewed changes
Copy link
Contributor

@aabadie aabadie left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Same changes as in #13179

ACK

@fjmolinas fjmolinas merged commit 3b3e290 into RIOT-OS:2020.01-branch Jan 28, 2020
@fjmolinas fjmolinas deleted the backport/2020.01/pr_openocd_stm32f7_probe branch January 28, 2020 10:22
This was referenced Feb 28, 2020
Merged
Closed
Closed
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Reviewers

@aabadie aabadie aabadie approved these changes

Assignees
No one assigned
Labels
CI: ready for build If set, CI server will compile all applications for all available boards for the labeled PR Process: release backport Integration Process: The PR is a release backport of a change previously provided to master Type: bug The issue reports a bug / The PR fixes a bug (including spelling errors)
Projects
None yet
Milestone
No milestone
Development

Successfully merging this pull request may close these issues.
2 participants
@fjmolinas @aabadie