esp32c3: ziscr extention missing #19421
Description
Description
When trying to use my brand new esp32c3, I ran into an issue compiling for it.
/pkg/esp32_sdk/components/hal/esp32c3/include/hal/interrupt_controller_ll.h:36: Error: unrecognized opcode `csrrc s0,mstatus,8', extension `zicsr' required
Others as well. All related to missing isa extensions.
Steps to reproduce the issue
- use 22.04.1-Ubuntu
- go to examples/hello-world (maybe add the esp-sdk pkg)
- run
BOARD=esp32c3-devkit make flash - Observe compilation errors
Expected results
Plug & Play, Build & Flash
This might be related to #17951
Given that PR, I replaced all occurrences of -march=rv32imc with -march=rv32imac_zicsr. That worked, I can compile, flash and see the hello world on my tty.
Additionally, I had to disable certain compiler warnings:
CFLAGS += -Wno-enum-conversion
CFLAGS += -Wno-attributes
CFLAGS += -Wno-maybe-uninitializedI also noticed this little message from the booting device:
# Calculated: 363da575129f253d18d4fc05a75bcfffe9a08e52786188f5f5d06a74cfd5bad5
# Expected: cb0f9786add2bad1adce930935dcb7a3ff28232451b0d3cd6255a9101fff41fa
# Attempting to boot anyway...
Not sure if relevant, as I'm new to esp32c3.
Click me: all rv32imc -> rv32imac_zicsr replacements
diff --git a/makefiles/arch/riscv.inc.mk b/makefiles/arch/riscv.inc.mk
index 3544b214b1..ed78a2bc05 100644
--- a/makefiles/arch/riscv.inc.mk
+++ b/makefiles/arch/riscv.inc.mk
@@ -44,12 +44,13 @@ ifeq (,$(TARGET_ARCH))
endif
ifeq ($(TOOLCHAIN),gnu)
- GCC_DEFAULTS_TO_NEW_RISCV_ISA ?= $(shell echo "typedef int dont_be_pedantic;" | $(TARGET_ARCH)-gcc -march=rv32imac -mabi=ilp32 -misa-spec=2.2 -E - > /dev/null 2>&1 && echo 1 || echo 0)
+ GCC_DEFAULTS_TO_NEW_RISCV_ISA ?= $(shell echo "typedef int dont_be_pedantic;" | $(TARGET_ARCH)-gcc -march=rv32imac_zicsr -mabi=ilp32 -misa-spec=2.2 -E - > /dev/null 2>&1 && echo 1 || echo 0)
endif
+
GCC_DEFAULTS_TO_NEW_RISCV_ISA ?= 0
-CFLAGS_CPU := -march=rv32imac -mabi=ilp32
+CFLAGS_CPU := -march=rv32imac_zicsr -mabi=ilp32
diff --git a/cpu/esp32/esp-idf/esp_idf_cflags.mk b/cpu/esp32/esp-idf/esp_idf_cflags.mk
index 3e7ac6b896..aafe2ea2da 100644
--- a/cpu/esp32/esp-idf/esp_idf_cflags.mk
+++ b/cpu/esp32/esp-idf/esp_idf_cflags.mk
@@ -35,7 +35,7 @@ CFLAGS += -Wno-cast-align
ifneq (,$(filter riscv32%,$(TARGET_ARCH)))
INCLUDES += -I$(ESP32_SDK_DIR)/components/riscv/include
CFLAGS += -DCONFIG_IDF_TARGET_ARCH_RISCV
- CFLAGS += -march=rv32imc
+ CFLAGS += -march=rv32imac_zicsr
CFLAGS += -Wno-error=format=
CFLAGS += -nostartfiles
CFLAGS += -Wno-format
diff --git a/cpu/esp32/bootloader/Makefile b/cpu/esp32/bootloader/Makefile
index dfb4a5df06..b56655cbfe 100644
--- a/cpu/esp32/bootloader/Makefile
+++ b/cpu/esp32/bootloader/Makefile
@@ -167,7 +167,7 @@ CFLAGS = -include '$(RIOTBUILD_CONFIG_HEADER_C)' \
ifneq (,$(filter riscv32%,$(TARGET_ARCH)))
INCLUDES += -I$(ESP32_SDK_DIR)/components/riscv/include
CFLAGS += -DCONFIG_IDF_TARGET_ARCH_RISCV
- CFLAGS += -march=rv32imc
+ CFLAGS += -march=rv32imac_zicsr
CFLAGS += -Wno-error=format=
CFLAGS += -nostartfiles
CFLAGS += -Wno-format
diff --git a/cpu/esp32/Makefile.include b/cpu/esp32/Makefile.include
index 956a132e2f..4167204fb0 100644
--- a/cpu/esp32/Makefile.include
+++ b/cpu/esp32/Makefile.include
@@ -206,7 +206,7 @@ CFLAGS += -D_CONST=const
# TODO no relaxation yet
ifneq (,$(filter riscv%,$(TARGET_ARCH)))
- CFLAGS += -mno-relax -march=rv32imc -mabi=ilp32 -DRISCV_NO_RELAX
+ CFLAGS += -mno-relax -march=rv32imac_zicsr -mabi=ilp32 -DRISCV_NO_RELAX
endif
ifneq (,$(filter xtensa%,$(TARGET_ARCH)))