build system: Fix compilation for RISC-V with newer GCC #17951
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A backward incompatible change in the RISC-V resulting in instructions previously included by rv32imac to only be available with rv32imac_zicsr. All RISC-V CPUs supported by RIOT are hence either considered as rv32imac (from the old ISA spec point of view) or as rv32imac_zicsr (from the new ISA spec point of view). This adds a simple test if GCC understands rv32imac_zicsr and uses it then as march, but uses rv32imac as march if not.
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@fabian18, @miri64, or @kaspar030 : You are using Arch, right? That one is also recent enough to no longer work. Note: It uses the |
If you tell me, which package I need to install on Arch to build this, I can test it. |
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I think when you install riscv32-elf-newlib it will pull in riscv64-linux-gnu-gcc and riscv64-elf-binutils as dependencies automatically. So just installing newlib for RISC-V should be fine. |
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I installed all three packages, you have metioned.
But there is something not right.
$ BOARD=hifive1b make
/bin/sh: -g: Ungültige Option
Aufruf: /bin/sh [Lange GNU-Option] [Option] ...
/bin/sh [Lange GNU-Option] [Option] Script-Datei ...
Lange GNU-Optionen:
--debug
--debugger
--dump-po-strings
--dump-strings
--help
--init-file
--login
--noediting
--noprofile
--norc
--posix
--pretty-print
--rcfile
--restricted
--verbose
--version
Shell-Optionen:
-ilrsD oder -c Kommando oder -O shopt_option (Nur Aufruf)
-abefhkmnptuvxBCHP oder Option -o
Building application "default" for "hifive1b" with MCU "fe310".
gcc: Fehler: nicht erkanntes Kommandozeilenargument in Option »-mabi=ilp32«
gcc: Anmerkung: gültige Argumente für »-mabi=« sind: ms sysv
gcc: Fehler: nicht erkanntes Kommandozeilenargument in Option »-mcmodel=medlow«
gcc: Anmerkung: gültige Argumente für »-mcmodel=« sind: 32 kernel large medium small
gcc: Fehler: unbekannte Kommandozeilenoption »-msmall-data-limit=8«
make[1]: *** [/home/fabian/forks/RIOT/Makefile.base:146: /home/fabian/forks/RIOT/examples/default/bin/hifive1b/application_default/main.o] Fehler 1
make: *** [/home/fabian/forks/RIOT/examples/default/../../Makefile.include:737: application_default.module] Fehler 2Omitting the middle part of `riscv32-none-elf` is apparently legal and done by Arch Linux.
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I'm getting the same. |
When no toolchain could be detected, provide a friendly message instead.
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OK, the issue is that it you need The build system spilled out the garbage when no toolchain was detected (the issue is present in Note: |
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Not using nanospecs but selecting https://gist.github.com/f1c3eb91b759e924782691cd9e75ba56 (digging out the qemu command line for testing) |
So, I'd blame Arch :) (But I could try to upstream a fix, though. After all, I have been a happy Archer myself for years.) |
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The issue with nano has just been fixed upstream. I guess by tomorrow you can test again on Arch with the updated package and it should just work fingers crossed. |
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I just did a system upgrade and |
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Thanks! |
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For me, with a riscv-gnu-toolchain this breaks linking: I don't think just checking the assembler ( If I bypass the check it works again for me but the autodetection is broken: --- a/makefiles/arch/riscv.inc.mk
+++ b/makefiles/arch/riscv.inc.mk
@@ -41,7 +41,7 @@ ifeq ($(TOOLCHAIN),gnu)
NEW_RISCV_ISA := $(shell echo "" | $(TARGET_ARCH)-as -march=rv32imac_zicsr -mabi=ilp32 - > /dev/null 2>&1 && echo 1 || echo 0)
endif
-NEW_RISCV_ISA ?= 0
+NEW_RISCV_ISA = 0
# Since RISC-V ISA specifications 20191213 instructions previously included in
# rv32imac have been moved to the ZICSR extension. See |
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@nmeum Sorry for the late reply. I can reproduce the issue with the current Arch Linux toolchain (apparently now there are ISA versions -1.-1, 2.0 and 2.1 into play). However, forcing I currently have no better solution that just waiting until the hole toolchain gets into a state of consistency again regarding the RISC-V ISA version. |
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One alternative solution might be explicitly specifying the ISA version used by RIOT. See the GCC documentation on RISC-V options. In that case, the following would need to be added to Version 2.2 is last specification standard where CSR support is still part of the base ISA (i.e. See also: https://groups.google.com/a/groups.riscv.org/g/sw-dev/c/aE1ZeHHCYf4/m/v88QeovDAAAJ |
Contribution description
A backward incompatible change in the RISC-V resulting in instructions previously included by rv32imac to only be available with rv32imac_zicsr. All RISC-V CPUs supported by RIOT are hence either considered as rv32imac (from the old ISA spec point of view) or as rv32imac_zicsr (from the new ISA spec point of view). This adds a simple test if GCC understands rv32imac_zicsr and uses it then as march, but uses rv32imac as march if not.
Testing procedure
When running
make BOARD=hifive1b -C examples/defaultwith newer GCC versions, one will see an error message similar to:With this PR, the compilation should work again, but also remain working with older GCC versions.
Issues/PRs references
None