ALAP/ASAP scheduler produces incorrect delays for circuits with classically controlled gates #7006
Description
Information
- Qiskit Terra version: 0.18.1
- Python version: 3.8.3
- Operating system: Windows 10
What is the current behavior?
The ALAP and ASAP schedulers give wrong delays for circuits with gates with a classical condition. This is because the passes do not respect topological order of classical bit lines, which they should.
Steps to reproduce the problem
from qiskit.circuit import QuantumCircuit
from qiskit import QuantumRegister, ClassicalRegister
from qiskit.transpiler.passes import ALAPSchedule
from qiskit.transpiler import PassManager, InstructionDurations
# Initialize a pass for an ALAP schedule
durations = InstructionDurations([('measure', None, 1), ('x', None, 1)])
alap = ALAPSchedule(durations)
pm_alap = PassManager(alap)
# Create test circuit
qreg = QuantumRegister(2, "q")
creg = ClassicalRegister(1, "c")
qc = QuantumCircuit(qreg, creg)
qc.measure(0, 0)
qc.x(1).c_if(creg, 1)
qc.x(1)
print(qc) # Optional: print the circuit as a reference
# Run ALAP on test circuit
qc_bad = pm_alap.run(qc)
# Beware: the circuit renderer might be confusing, since the conditional X gate is rendered after the measurement.
# However according to the delay gates, the X gate conditioned on the classical bit happens before the measurement.
print(qc_bad)
What is the expected behavior?
The passes need to insert delays on qubits with gates conditioned on classical bits, such that those gates are always done later than the measurement producing the classical bit outcome. The correct topological order for conditional gates is already present in the DAGCircuit, so one should only need to fix the passes.
Suggested solutions
Treat qubits and clbits on equal footing. This means variables such as qubit_time_available in the pass run method should keep track of time for clbits too.