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Gates are not left justified in mpl circuit drawer #2788

@nonhermitian

Description

@nonhermitian

Information

  • Qiskit Terra version: master
  • Python version:
  • Operating system:

What is the current behavior?

There is always a space on the line between the qubit label and the first gate:
circ_color

To reduce the width of the figure as much as possible, the gates should be drawn as far left as possible.

Steps to reproduce the problem

What is the expected behavior?

Suggested solutions

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