[CPU] Update custom ops for the CPU backend #20255

bigPYJ1151 · 2025-06-30T12:46:17Z

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The purpose of the PR, such as "Fix some issue (link existing issues this PR will resolve)".
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The test results, such as pasting the results comparison before and after, or e2e results
(Optional) The necessary documentation update, such as updating supported_models.md and examples for a new model.

Purpose

Update the CPU backend custom ops include:

Optimize shared-memory based AllReduce
Adapt small-batch optimized GEMM and Grouped-GEMM for linear layers and MoE layers, from sglang-cpu
Enable corresponding tests
Update doc

Test Plan

Test Result

(Optional) Documentation Update

Signed-off-by: jiang1.li <jiang1.li@intel.com>

gemini-code-assist

Summary of Changes

Hello @bigPYJ1151, I'm Gemini Code Assist¹! I'm currently reviewing this pull request and will post my feedback shortly. In the meantime, here's a summary to help you and other reviewers quickly get up to speed!

This pull request updates the CPU backend with several optimizations, including improvements to AllReduce, GEMM, and Grouped-GEMM operations. It also adds support for AVX512-BF16 and AVX512VNNI instruction sets, along with corresponding tests and documentation updates. The changes aim to improve the performance and efficiency of the CPU backend, especially for small-batch sizes and MoE layers.

Highlights

CPU Backend Optimization: Optimized shared-memory based AllReduce for CPU backend.
GEMM and Grouped-GEMM Adaptation: Adapted small-batch optimized GEMM and Grouped-GEMM from sglang-cpu for linear and MoE layers.
AVX512-BF16 and AVX512VNNI Support: Added support for AVX512-BF16 and AVX512VNNI instruction sets, including detection and compilation flags.
Test Updates: Enabled corresponding tests for the new CPU backend features.
Buildkite Configuration: Increased the timeout for CPU tests in Buildkite to 1.5 hours.

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Code Review

This pull request introduces optimizations for CPU inference by integrating custom kernels from sglang for small-batch GEMM and MoE operations, and refactors the shared memory communication layer. The changes are substantial and well-executed. My review includes suggestions for removing debug code, improving code comments for the new synchronization logic, and adding user-friendly checks for the new kernel requirements. Overall, this is a great enhancement for vLLM's CPU backend.

gemini-code-assist · 2025-06-30T12:50:59Z

csrc/cpu/sgl-kernels/gemm.h

+inline void print_16x32i(const __m512i x) {
+  int32_t a[16];
+  _mm512_storeu_si512((__m512i *)a, x);
+
+  for (int i = 0; i < 16; i++){
+    std::cout << a[i] << " ";
+  }
+  std::cout << std::endl;
+}
+
+inline void print_16x32(const __m512 x) {
+  float a[16];
+  _mm512_storeu_ps((__m512 *)a, x);
+
+  for (int i = 0; i < 16; i++){
+    std::cout << a[i] << " ";
+  }
+  std::cout << std::endl;
+}
+
+
+inline void print_32x8u(const __m256i x) {
+  uint8_t a[32];
+  _mm256_storeu_si256((__m256i *)a, x);
+
+  for (int i = 0; i < 32; ++i) {
+    std::cout << int32_t(a[i]) << " ";
+  }
+  std::cout << std::endl;


These debug print functions should be removed before merging. The TODO comment indicates they are temporary. Leaving them in adds unnecessary code to the binary and could be confusing for future maintenance.

gemini-code-assist · 2025-06-30T12:50:59Z

vllm/model_executor/layers/fused_moe/layer.py

+                if (envs.VLLM_CPU_SGL_KERNEL
+                        and torch._C._cpu._is_amx_tile_supported()
+                        and dtype == torch.bfloat16):


The SGL kernels have alignment requirements for the weight tensor dimensions. Add checks here for the MoE layer weights (w13_weight and w2_weight) to ensure their dimensions are divisible by the required tile sizes (e.g., 32).

This would provide a more user-friendly warning if the model is not compatible, rather than failing with a TORCH_CHECK from the C++ code.

Suggested change

if (envs.VLLM_CPU_SGL_KERNEL

and torch._C._cpu._is_amx_tile_supported()

and dtype == torch.bfloat16):

if (envs.VLLM_CPU_SGL_KERNEL

and torch._C._cpu._is_amx_tile_supported()

and dtype == torch.bfloat16):

_, N2, K = layer.w13_weight.shape

N = N2 // 2

if K % 32 != 0 or N % 32 != 0:

logger.warning(

"CPU SGL kernels for MoE require K and N dims to be multiples of 32. "

"Disabling SGL kernels.")

layer.cpu_fused_moe = cpu_fused_moe.IPEXFusedMOE(layer)

return

github-actions · 2025-06-30T12:57:09Z

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bigPYJ1151 · 2025-07-01T04:35:42Z

Hi @DarkLight1337 @Isotr0py , would you please help to check this PR? Thanks :)

There are lots of new added code but most are CPU-specific only. The changes on vLLM core components are limited. And both of the fast checks and the CPU test passed.

Signed-off-by: jiang1.li <jiang1.li@intel.com>

Signed-off-by: jiang1.li <jiang1.li@intel.com> Signed-off-by: avigny <47987522+avigny@users.noreply.github.com>

Signed-off-by: jiang1.li <jiang1.li@intel.com> Signed-off-by: Jinzhen Lin <linjinzhen@hotmail.com>

Signed-off-by: jiang1.li <jiang1.li@intel.com>

bigPYJ1151 added 5 commits June 30, 2025 12:36

disable custom ops when using inductor

68f6973

Signed-off-by: jiang1.li <jiang1.li@intel.com>

update shm

99b2ebf

Signed-off-by: jiang1.li <jiang1.li@intel.com>

add sgl kernels

0620cc0

Signed-off-by: jiang1.li <jiang1.li@intel.com>

enable tests

8b32ddb

Signed-off-by: jiang1.li <jiang1.li@intel.com>

update doc

ca5433b

Signed-off-by: jiang1.li <jiang1.li@intel.com>

bigPYJ1151 requested review from hmellor, DarkLight1337 and ywang96 as code owners June 30, 2025 12:46

mergify bot added documentation Improvements or additions to documentation ci/build labels Jun 30, 2025

gemini-code-assist bot reviewed Jun 30, 2025

View reviewed changes

DarkLight1337 approved these changes Jul 1, 2025

View reviewed changes

DarkLight1337 enabled auto-merge (squash) July 1, 2025 04:46

github-actions bot added the ready ONLY add when PR is ready to merge/full CI is needed label Jul 1, 2025

Isotr0py approved these changes Jul 1, 2025

View reviewed changes

DarkLight1337 merged commit 6cc1e7d into vllm-project:main Jul 1, 2025
109 checks passed

CSWYF3634076 pushed a commit to CSWYF3634076/vllm that referenced this pull request Jul 2, 2025

[CPU] Update custom ops for the CPU backend (vllm-project#20255)

50ba35d

Signed-off-by: jiang1.li <jiang1.li@intel.com>

bigPYJ1151 mentioned this pull request Jul 3, 2025

[CI/Build][CPU] Enable cross compilation in CPU release pipeline #20423

Merged

4 tasks

avigny pushed a commit to avigny/vllm that referenced this pull request Jul 31, 2025

[CPU] Update custom ops for the CPU backend (vllm-project#20255)

d617aef

Signed-off-by: jiang1.li <jiang1.li@intel.com> Signed-off-by: avigny <47987522+avigny@users.noreply.github.com>

jinzhen-lin pushed a commit to jinzhen-lin/vllm that referenced this pull request Aug 9, 2025

[CPU] Update custom ops for the CPU backend (vllm-project#20255)

6309f9b

Signed-off-by: jiang1.li <jiang1.li@intel.com> Signed-off-by: Jinzhen Lin <linjinzhen@hotmail.com>

googlercolin pushed a commit to googlercolin/vllm that referenced this pull request Aug 29, 2025

[CPU] Update custom ops for the CPU backend (vllm-project#20255)

26c52c5

Signed-off-by: jiang1.li <jiang1.li@intel.com>

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[CPU] Update custom ops for the CPU backend #20255

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-                if (envs.VLLM_CPU_SGL_KERNEL
-                        and torch._C._cpu._is_amx_tile_supported()
-                        and dtype == torch.bfloat16):
+                if (envs.VLLM_CPU_SGL_KERNEL
+                        and torch._C._cpu._is_amx_tile_supported()
+                        and dtype == torch.bfloat16):
+                    _, N2, K = layer.w13_weight.shape
+                    N = N2 // 2
+                    if K % 32 != 0 or N % 32 != 0:
+                        logger.warning(
+                            "CPU SGL kernels for MoE require K and N dims to be multiples of 32. "
+                            "Disabling SGL kernels.")
+                        layer.cpu_fused_moe = cpu_fused_moe.IPEXFusedMOE(layer)
+                        return

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