An implementation of a CPU that uses a Linear Feedback Shift Register as a Program Counter instead of a normal one

🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.

This project aims to test how fast you can respond after seeing a visual stimulus or rather hand-eye coordination.

Comprehensive Random Number Generator implementation featuring both Pseudo-Random Number Generator (PRNG) using Linear Feedback Shift Registers and True Random Number Generator (TRNG) using Ring Oscillators

RTL descriptions and test benches for a virtual link

A vhdl device to generate random numbers LFSR

Koc University ELEC 204: Digital Design project

VHDL circuit testing project featuring scan-based TRCUT architecture with testbenches, LFSR-based pseudorandom input generation, MISR-based signature analysis with fault injection (stuck-at and transient), and full IEEE 1149.1 (JTAG) implementation with TAP controller and boundary scan.