Fault tolerant FIR filter designed using N-modular redundancy technique for creating hardware fault tolerance
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Updated
Nov 25, 2017 - VHDL
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fault-injection
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Post-manufacturing test analysis
compression decompression testing-tools fault-injection atpg bist jtag-boundary-scan mbist testability-analysis scan-chain fault-collapsing design-for-test
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Mar 27, 2024 - VHDL
VHDL circuit testing project featuring scan-based TRCUT architecture with testbenches, LFSR-based pseudorandom input generation, MISR-based signature analysis with fault injection (stuck-at and transient), and full IEEE 1149.1 (JTAG) implementation with TAP controller and boundary scan.
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Jul 10, 2025 - VHDL
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