Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

Notes on the Red Pitaya Open Source Instrument

PYNQ Composabe Overlays

DMA attacks over PCI Express based on Xilinx Zynq-7000 series SoC

Xilinx PCIe to MIG DDR4 example designs and custom part data files

TCL scripts for FPGA (Xilinx)

Building linux kernel and u-boot for MYIR Z-Turn 7020 Zynq Board

PYNQ-Z1 Compatible Python helper functions for AXI UARTLITE IP Core of Xilinx

SEM (Soft Error Mitigation) IP adapted for PYNQ-Z2

Case study of synchronous FPGA signaling by adjusting the output timing

HLS-based Xilinx ICAP3 Controller (tested with VCU108)

Simple audio processing with ADAU1761

some reusable scripts

Basic JTAG / AXI demonstration on Xilinx's FPGA.

Project template for Xilinx-based FPGA designs

VHDL UART Module with AXI interface

A repository of example projects for the Red Pitaya (Xilinx Zynq-7010) to complement a series of blog posts.

[NO DEVELOPMENT] Mellanox Innova-1 Flex Usage Notes+Guides for Kintex Ultrascale FPGA Development