Pre-v6 ARM targets (except for Linux) don't support atomic CAS.

As far as I know, there are several ways to support this:

• Spinlock based on SWP instruction. (multi-core safety: yes)
  implementation: Support atomic CAS on no-std pre-v6 ARM using SWP instruction #27
  EDIT: this is broken on single-core + interrupt situations

• Disabling interrupts. (What we are currently doing for thumbv6m and other targets.) (multi-core safety: no)
  Is there a standardized way to do this? Maybe interrupt disable bits in CPSR?
  implementation: interrupt: Support no-std pre-v6 ARM targets #28

• Use atomic builtins. (Let the user implement the actual atomic logic.) (multi-core safety: implementation-dependent)
  See this comment for problems I am aware of.
  implementation: Add cfg to use __atomic_* builtins #30

• Optional feature to use 3rd party crate like critical-section. (Let the user implement the actual atomic logic.) (multi-core safety: no by default)
  However, critical-section 0.2 should be enabled only under the unsafe cfg because the default implementation is unsound on multi-core systems.
  Even on critical-section 1.0, it seems that this also needs to be unsafe because it has the same problems as the case using atomic builtins.