You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
{{ message }}
This repository was archived by the owner on Mar 2, 2023. It is now read-only.
Version 0.7.0
- Bump Chisel to 3.5.5
- Bump CIRCT to 1.22.1
- Add support for Chisel's Trace API
- Improve APIs for passing options to circt.stage.ChiselStage
v0.5.0 Release
Updates to align with SiFive v1.11.0 version of CIRCT:
- Use new firtool CLI options
- Add an option for enabling aggregate preservation
- Bridge EmitAllModules to split Verilog emission
0.3.0 Release
This roughly aligns with v0.0.7 release of CIRCT. The major changes of
this release are as follows:
- Annotations are passed to CIRCT
- The default handover point is now CHIRRTL
- Scala 2.13 is now published in addition to Scala 2.12
This marks the first truly usable version of chisel-circt because CIRCT
has implemented all necessary passes of a FIRRTL compiler. At this
time, common annotations/non-default transforms are supported including
"do not touch", inlining/flattening, and forced module names.
0.2.0 Release
- Aligns with newer "firtool" API of "-lower-types". Previously this
was "-enable-lower-types".
- Add "-target verilog" option.
- Bump dependencies to latest published versions.