The issue manifested itself when comparing the delay of PCBs between beacon servers that don't have well synchronized clocks. Imaging two ASes A and B and the clock of the BS in B is 500ms behind of A's. End-to-end latency between BS A and BS B is 50ms. This will lead to a negative delay parameter of ~450ms since the clock in BS A is 500ms ahead.

However, the issue goes deeper and potentially affects all the time comparisons that we do, e.g., for certificate validity or revocations. We should allow for some amount of clock drift in both directions. The exact parameter of how much drift can be allowed needs to be determined.