What's Changed

• [rtl] derive all memories from generic RAM primitives by @stnolting in #1347
• [rtl] add all-new FIFO primitive by @stnolting in #1349
• [demo_semihosting] use 4-byte instead of 16-byte alignment by @vogma in #1350
• 🐛 fix simulation memory-component by @stnolting in #1352
• ⚠️ simplify SLINK, SPI and NEOLED modules by @stnolting in #1353
• ⚠️ simplify UART and SDI modules by @stnolting in #1354
• simplify ROM images (VHDL packages for IMEM/BOOTROM) by @stnolting in #1355
• [rtl] minor code-cleanups and optimizations by @stnolting in #1357
• [sdi] add RX & TX FIFO clear flags by @stnolting in #1358
• ⚠️ rework TWD module by @stnolting in #1359
• fix minor RISC-V incompatibilities by @stnolting in #1360

Full Changelog: v1.12.0...v1.12.1

What's Changed

• ⚠️ [CPU] remove double-trap exception by @stnolting in #1332
• minor fixes and optimizations by @stnolting in #1333
• Add NEORV32-specifc "machine control and status" CSR (mxcsr) by @stnolting in #1335
• Add new tuning option: Constant-time branches by @stnolting in #1338
• Rework bus access error logic by @stnolting in #1339
• ⚠️ [SYSINFO] rework layout of "MISC" information register by @stnolting in #1342
• [rtl] replace individual IMEM & DMEM modules by a generic memory component by @stnolting in #1344
• [Vivado IP] Remove relative paths from the IP-packaging script by @stnolting in #1341
• rtl code cleanups and optimizations by @stnolting in #1345
• 🐛 [dma] fix byte-enable signal for byte-reads by @stnolting in #1346

Full Changelog: v1.11.9...v1.12.0

What's Changed

• 🐛 fix double-trap tracking bug by @stnolting in #1312
• ✨ add new module: execution trace buffer (TRACER) by @stnolting in #1313
• Cleanup UART simulation logging by @stnolting in #1314
• Replace trace with trace_s in the top by @Unike267 in #1316
• Add GDB tracer support by @stnolting in #1317
• [tracer] write full trace log to file by @stnolting in #1318
• ✨ add support for RISC-V Zcb ISA extension by @stnolting in #1320
• extend tracer simulation log; improve semihosting by @stnolting in #1322
• Make cache/AXI bursts optional by @stnolting in #1324
• Minor rtl edits and cleanups by @stnolting in #1325
• minor rtl edits and cleanups by @stnolting in #1331

Full Changelog: v1.11.8...v1.11.9

New Features

• add double-trap exception (loosely based on the RISC-V Smdbltrp ISA extension)
• add support for hardware-assisted watchpoints (on-chip debugger)
• add configurable number of hardware break-/watchpoint (0..16)

What's Changed

• remove WDT "strict" bit; minor code edits and cleanups by @stnolting in #1293
• 🧪 add double-trap exception by @stnolting in #1294
• Rework RTE trap handler look-up-table by @stnolting in #1295
• [rte] cleanups and optimizations by @stnolting in #1299
• minor rtl edits and cleanups by @stnolting in #1302
• Feature: Libero support by @hughbreslin in #1300
• [ocd] add support for hardware watchpoints by @stnolting in #1303
• ✨ add configurable number of break-/watchpoints by @stnolting in #1304
• minor rtl edits and cleanups by @stnolting in #1307
• ⚠️ [top] remove HART_BASE generic by @stnolting in #1308
• [cache] fix minimal cache block size by @stnolting in #1310

New Contributors

• @hughbreslin made their first contribution in #1300

Full Changelog: v1.11.7...v1.11.8

What's Changed

• [cpu] Minor rtl optimizations and cleanups by @stnolting in #1283
• upgrade TRNG to neoTRNG v3.3 by @stnolting in #1284
• ✨ on chip debugger: add semihosting support by @stnolting in #1285
• ⚠️ combine SLINK's RX and TX interrupts into a single interrupt by @stnolting in #1286
• ✨ add TRNG interrupt by @stnolting in #1287
• ⚠️ rework UART "TX FIFO full" status flag by @stnolting in #1288
• ⚠️ combine UART's RX and TX interrupts into a single interrupt by @stnolting in #1289
• Minor rtl edits and optimizations by @stnolting in #1291
• Remove enable logic for SoC-wide clock generator by @stnolting in #1292

Full Changelog: v1.11.6...v1.11.7

What's Changed

• 🐛 fix byte-enable bus signal for instruction fetch accesses by @stnolting in #1272
• minor rtl edits and cleanups by @stnolting in #1273
• ⚠️ CFS IO rework by @stnolting in #1274
• ⚠️ remove CRC module by @stnolting in #1275
• Rework IMEM & DMEM RAM style by @stnolting in #1277
• [cpu] rework instruction trap logic by @stnolting in #1278
• 🧪 rework DMA controller by @stnolting in #1279
• ⚠️ Rename IMEM/DMEM configuration generics by @stnolting in #1280
• Add optional IMEM/DMEM output register stages by @stnolting in #1281

Full Changelog: v1.11.5...v1.11.6

What's Changed

• Rework caches; use "write-through" strategy by @stnolting in #1259
• Rework locking of processor-internal bus by @stnolting in #1260
• minor edits and optimizations by @stnolting in #1262
• ✨ add cache burst transfers by @stnolting in #1263
• [bus] add explicit burst signal to internal processor bus by @stnolting in #1265
• 🐛 Fix missing burst signal in bus register stage by @stnolting in #1266
• ⚠️ make MCAUSE CSR read-only by @stnolting in #1267
• ⚠️ [inter-processor communication] remove hardware spinlocks and inter-core communication links by @stnolting in #1268
• 🐛 fix CPU bus issues by @stnolting in #1270

Full Changelog: v1.11.4...v1.11.5

What's Changed

• Make hardware breakpoint optional; constrain to debug-mode only by @stnolting in #1239
• 🐛 [bootloader] fix privilege at application start by @stnolting in #1241
• Optimize round-robin bus switch: remove idle cycles by @stnolting in #1244
• Add bus lock feature by @stnolting in #1245
• Optimize cache system by @stnolting in #1248
• Rework newlib system calls by @stnolting in #1249
• ⚠️ Rework processor-internal bus protocol by @stnolting in #1252
• Add full-scale AXI4 bridge by @stnolting in #1253
• [docs] fix dead link to setups by @josuah in #1255
• ⚠️ Remove external bus interface cache (xbus-cache) by @stnolting in #1256
• ⚠️ Rework cache configuration options by @stnolting in #1257

New Contributors

• @josuah made their first contribution in #1255

Full Changelog: v1.11.3...v1.11.4

What's Changed

• [docs] inline Wavedrom scripts by @stnolting in #1208
• docs: datasheet: cpu: fix name for the "A" ISA extension by @henrikbrixandersen in #1209
• build: rebuild exe when header files change by @ecstrema in #1212
• fix litex boot by @pepijndevos in #1211
• ⚠️ Remove CPU clock gating option by @stnolting in #1214
• [rtl/sw] Add twd dummy byte, add twd bootloader and smaller fixes by @LukasP46 in #1210
• ✨ Add 32 hardware spinlocks by @stnolting in #1220
• 🐛 fix PWM prescaler by @stnolting in #1222
• 🐛 [linker] fix alignment of init/fini arrays by @stnolting in #1224
• Minor rtl edits and optimizations by @stnolting in #1225
• [sw/lib] add restart/reset functions by @stnolting in #1226
• 🐛 [SDI] fix input synchronizer by @stnolting in #1227
• [sw/lib/neoled] fix neoled "irq_mode" not a applied in "neorv32_neoled_setup" and [sw/lib/neoled] updated doxygen comments by @SirBramble in #1228
• Add support for setting PWM polarity by @henrikbrixandersen in #1230
• [sw] cleanup main software makefile, add git tag, add verbosity configuration by @stnolting in #1231
• [sw/bootloader] TWI fix for bootloader by @SirBramble in #1229
• Rework bootloader by @stnolting in #1215
• [rtl/pmp] fix multiple signal assignment by @NikLeberg in #1236
• [rtl/core/twi] delay sda low by @SirBramble in #1237

New Contributors

• @SirBramble made their first contribution in #1228

Full Changelog: v1.11.2...v1.11.3

What's Changed

• ✨ add support for Zalrsc ISA extension by @stnolting in #1181
• Minor rtl optimizations and cleanups by @stnolting in #1182
• Source-out CPU front-end by @stnolting in #1183
• ⚠️ Software libraries cleanup by @stnolting in #1186
• Fix Bootloader Makefile UART_BAUD by @lebruu in #1189
• 🐛 fix bug in Zalrsc ISA extension by @stnolting in #1190
• [rtl] minor edits and cleanups by @stnolting in #1191
• [cpu] relocate CPU counters by @stnolting in #1192
• minor rtl edits by @stnolting in #1193
• ⚠️ rework DMA and GPTMR by @stnolting in #1194
• rtl: processor_templates: enable Zicntr ISA extension on minimal templates by @henrikbrixandersen in #1196
• Fix: quote readlink to fix windows make check by @ecstrema in #1197
• fix: increment location counter with heap size by @brkydnc in #1201
• Add NUMA LiteX configuration by @pepijndevos in #1204
• 🐛 Fix Zbb shift instructions by @stnolting in #1206
• ⚠️ rename SPI & TWI transfer functions by @stnolting in #1207

New Contributors

• @lebruu made their first contribution in #1189
• @ecstrema made their first contribution in #1197
• @brkydnc made their first contribution in #1201
• @pepijndevos made their first contribution in #1204

Full Changelog: v1.11.1...v1.11.2