For installation instructions, see the README.

Added and improved architecture support:

• added support for MSP430/MSP430X architecture, as the first interpreted ISA in Renode

• ARM

  • added automatic connection of all ARM-A/R CPUs to GIC
  • added new registers for Cortex-A55
  • added definitions of Cortex-R5 specific CP15 registers
  • added TrustZone support for ARMv8-M
  • added FEAT_IDST support
  • added Thumb2 support on ARMv8
  • added support for 32-bit code in EL0
  • added ability to choose whether to emulate PSCI conduit with SMC or HVC
  • exposed 64 bit VFP registers
  • fixed RBAR/RLAR aliases by adding offset to the current region number
  • fixed a crash on not-completely initialized MMU mode
  • fixed issues with registers affecting code translation
  • fixed handling of the GE flag in sadd{8,16}, ssub{8,16}, usub{8,16} instructions
  • fixed Cortex-A78 core number value
  • fixed accessing 64-bit CSRs
  • fixed section descriptor decoding in LPAE
  • fixed PMSAv8 MPU control register behavior
  • fixed Cortex-M FPU context saving upon an IRQ
  • fixed swapping low and high portions of FPU registers on exception entry, when lazy preservation is not enabled
  • fixed wrong TB size reported for some Thumb instructions
  • fixed GICv3 CPU system registers incorrectly being enabled for older GIC versions
  • fixed access to system registers in 32-bit mode on a 64-bit core
  • fixed VFP instructions in 32-bit EL0 with 64-bit EL1
  • fixed a crash when performing a TLB fill while executing AArch32 code in certain conditions
  • fixed incorrect reporting of the IL field in the syndrome of data aborts taken to Hyp mode
  • fixed low bits of ATS1CP[RW] incorrectly treated as flags in the result (PAR) register
  • fixed handling of scalar VMOV
  • fixed the Thumb flag being set in block flags in traces in A64 state in some circumstances
  • changed lda/stl instructions on Armv8-M to not require address reservations as they are not exclusive
  • fixed PC synchronization in AArch64 state
  • improved SMC calls emulation
  • added non-secure aliases for v8 MPU (TrustZone)
  • reduced the verbosity of sysreg-related logs

• RISC-V

  • improved handling of the MSTATUS.FS flag
  • improved parsing of ISA strings to support more granular extension descriptions and custom extensions
  • fixed setting of the mtval register with the opcode that caused an exception
  • various fixes in Zb* Bit Manipulation instructions
  • fixed atomic LR/SC instructions
  • fixed incorrect log messages resulting from all-zero instruction translation
  • fixed the vmsbc instruction
  • fixed extension checking for compressed float load/store
  • added handling of the RV32E base integer instruction set in cpuType string parsing
  • added mirroring of the MCAUSE fields MPP and MPIE to MSTATUS in CLIC mode
  • added support for the Zacas extension for performing atomic Compare-and-Swap (CAS) operations
  • added support for Zve* and Zvfh vector extensions

• added support for single vector trapping in selected SPARC cores

• added mechanism for dynamic ACPI table generation in X86

• added initial SMP support for x86

• added initial x86 KVM-based CPU support

Added and improved platform descriptions:

• ZynqMP UltraScale+ with ZCU102 and ZCU104 boards
• Renesas RZ/G2L
• Silicon Labs Series-2- xG24, xG26, xG22 with a range of peripherals, including xG24 radio
• BeagleV Fire
• Polarfire SoC with Icicle Kit
• Atmel SAM4S8B
• Atmel SAM4S16C with SAM4S XPLAINED
• Atmel SAMD21J17D
• NXP IMXRT500
• NXP Layerscape lx2160ardb
• Nuvoton NPCX9
• UP Squared
• Virtualized x86 KVM
• LiteX-based platforms

Added demos:

• MSP430F2619 Hello World demo
• BeagleV-Fire booting up Linux Buildroot
• Contiki-NG Hello World demo for Zolteria Z1
• Web server running in Docker on ZynqMP
• SAM4S series based demo running Zephyr shell sample
• i386 KVM Linux demo
• i386 KVM U-Boot demo
• Renesas RZ/G2L Linux demo
• Renesas RZ/G2L U-Boot based demo
• lx2160ardb U-Boot based demo
• IMXRT500 demo running Zephyr's shell_module sample
• UP Squared demo running Zephyr's hello_world sample
• NXP S32K388 demo running Zephyr's shell module sample
• VeeR_EL2 Tock OS demo

Added tests:

• infrastructure for GDB testing in Robot
• 32-bit userspace with 64-bit kernel on ZynqMP
• Cortex-M FPU context saving upon an IRQ
• 64 bit VFP Arm registers access test
• IMXRT500 test running Pigweed bluetooth advertiser
• SAM4S XPLAINED Zephyr blinky and button
• RISC-V LR/SC operations
• MSP430F2619 memory read
• i386 KVM Linux
• i386 KVM U-Boot
• Renesas RZ/G2L MHU
• Renesas RZ/G2L Linux
• Renesas RZ/G2L U-Boot
• VexRiscv CFU
• lx2160ardb U-Boot
• VeeR_EL2 Tock OS
• UP Squared test running Zephyr hello_world sample
• NXP S32K388 test running Zephyr shell module sample
• Zephyr tickless_kernel test suite on Icicle Kit with ZephyrMode skipped
• Zephyr LLEXT test on ARM Cortex-R8
• LLVM assembler
• LLVM assemble and disassemble test for rv32gc_xandes
• code execution from ArrayMemory
• verification of selective memory range caching
• SystemC cosimulation
• fetching symbols in Monitor and Python
• timestamp based variant of RESD tests for AK09918 sensor
• execution_tracer LCOV format
• CPU hooks on addresses backed by ArrayMemory
• autocompletion tests
• instructions counting tests
• REPL using statement test
• LogFunctionNames filtered symbol LUT unit test

Added features:

• support for creating .NET packages for Debian, Fedora and Arch
• support for running Renode natively on Aarch64 macOS and Linux
• atomic instrinsics for Aarch64 hosts
• assembler and disassembler for MSP430
• U-Boot Mode support for Arm, Arm-M and RISC-V
• SystemCCPU model in SystemCPlugin
• wrapper for a Cortex-M CPU in SystemCPlugin
• dynamic TCP ports allocation for SystemC co-simulation
• custom include directories in SystemC integration build
• sharing a single connection by multiple co-simulated peripherals, allowing for more complex scenarios supported by a single simulator instance
• LLVM assembler and dissasembler support for Aarch64 hosts
• PeakRDL plugin for generating models stubs based on RDL
• PeakRDL plugin for generating platform description files from RDL
• alternative profile collection based on stack pointer changes, available in collapsed stack profiling
• support for code execution from ArrayMemory
• support for changing peripheral access conditions at runtime
• Wait For Gdb Connection Robot keyword, to await a GDB connection to a GDB server running on a specific port
• WriteToClear mode for register fields
• WriteToSet mode for register fields
• configurable mechanism for caching of consecutive reads from a single address, to improve performance of register polling
• Bus Isolation concept to filter access to peripherals based on the bus transaction state
• parameter to ZephyrMode plugin allowing it to skip ZephyrMode for provided symbols
• keyword argument support for Monitor Python commands (kwargs)
• access to Monitor variabless in Python scripts
• support for creating testers on externals
• support for multiple HDL controllers and peripherals connected to a single renode module without an interconnect
• support for detecting strings that will fail a test
• support for the reset attribute in REPL files, which will be executed for each peripheral upon machine reset
• arbitrary timestamp block support for RESD
• config window-allow-outside-viewport to control the behavior of snapping to a visible portion of the screen
• config window-initial-offset-{x,y} for configuring initial Renode Window position from screen edge
• mechanism for sending signals from Renode to DPI peripherals
• time skip hook for an arbitrary symbol
• the if helper function for Monitor
• support for passing array arguments using [1, 2] syntax in the Monitor, positional and named alike, including params T[]
• option for synchronous execution tracing
• option to limit maximum profile trace file size
• option to limit maximum number of nested thread contexts in profilers
• option to load a binary starting from a specified offset
• ability to wait for a byte-encoded string with the TerminalTester
• ability to assemble instructions into memory from the Monitor
• ability to disassemble x86 instructions using the Intel syntax
• ability to feed UART with arbitrary binary data using RESD files
• explicit ports assignment in connection to HDL co-simulation
• memory dumping to file in binary and Intel hex formats
• coloring option for the network logger
• option to load a string as bytes into memory
• custom Python hooks for handling SMC instruction
• API for accessing CPU registers by name in Python
• binary data sample type for RESD
• socket UART analyzer
• new instructions atomic_fetch_add_intrinsic_i32/64 in code generator
• support for Coverview in Execution Tracer
• support for the LCOV format in Execution Tracer
• Execution Tracer option to process multiple trace files and produce a desc file with aggregated results

Changed:

• improved compatibility with HDL simulators of the DPI integration
• replaced temporary file overwrite mechanism with directory removal
• temporary files path is now configurable
• significantly sped up coverage report generation via execution_tracer
• log aggregation is now performed at the Logger level for all backends
• dynamically compiled assemblies are now loaded right away after compilation to reduce the usage of 'EnsureTypeIsLoaded'
• a failing Python command is now reported in the Monitor when ran interactively
• added optional signals for APB3 in integration with Verilator
• added validation of signal connections in integration with Verilator
• the ...

For installation instructions, see the README.

Added and improved architecture support:

• fixed Arm MPU skipping access checks for MPU regions sharing a page with a background region
• FPU dirty flag is now set on all FPU load instructions for RISC-V
• fixed Arm PMSAv8 not checking for domains not being page aligned
• RISC-V MTVAL register now contains the invalid instruction after illegal instruction exception
• Arm SRS (Store Return State) instruction now saves onto stack SPSR instead of masked CPSR
• improved support for x86-64, verified with Zephyr
• added SMEPMP extension stub for RISC-V
• added ability to configure usable bits in RISC-V PMPADDR registers
• fixed runtime configurability of the RISC-V MISA registers
• fixed RISC-V PMPCFG semantics from WIRI to WARL
• fixed decoding of C.ADDI4SPN in RISC-V
• fixed behavior of RORIW, RORI and SLLI.UW RISC-V instructions
• changed MSTATUS RISC-V CSR to be more responsive to the presence of User and Supervisor modes

Added and improved platform descriptions:

• NXP MR-CANHUBK3
• NXP S32K388
• NXP S32K118
• RI5CY
• Renesas r7fa8m1a
• Renesas DA14592
• STM32H743
• x86-64 ACRN

Added demos and tests:

• Zephyr running hello_world demo on x86-64 ACRN
• ZynqMP demo showcasing two way communication between Cortex-A53 running Linux and Cortex-R5 running OpenAMP echo sample

Added features:

• Socket Manager mechanism, organizing socket management in a single entity
• test real-time timeout handling mechanism in Robot
• GPIO events support for the External Control API
• Zephyr Mode support for Arm, Arm-M, SPARC, x86 and Xtensa
• disassembling support for x86-64 architecture
• support for bus access widths other than DoubleWord for DPI integration of APB3
• support for overriding a default implementation of the verilated UART model

Changed:

• improved renesas-segger-rtt.py helper
• Renode logs a warning instead of crashing when HDL co-simulated block reports an error
• improved guest cache tool results readability

Fixed:

• PulseGenerator behavior when onTicks == offTicks
• External Control API GetTime command returning incorrect results
• SystemC integration crashing when initializing GPIO connections
• USB Speed value reported in USB/IP device descriptor
• USB endpoints with the same number but opposite direction not being distinguished
• a potential crash due to OverflowException when stopping the emulation
• checking address range when mapping memory ranges in TranslationCPU
• configuration descriptor parsing in USBIPServer
• fatal TCG errors in some cases of invalid RISC-V instructions
• handling registration of regions not defined by peripherals
• handling registration of regions with unpaired access method
• incorrect sequence number in USBIP setup packet reply
• SD card reset condition
• starting GDB stub on platforms containing CPUs not supporting GDB
• infinite loop on debug exception with an interrupt pending
• simulation elements unpausing after some Monitor commands

Added peripheral models:

• Arm CoreLink Network Interconnect
• LPC Clock0
• RenesasDA14 GeneralPurposeRegisters
• STM32 SDMMC
• Synopsys SSI

Improvements in peripherals:

• Arm Signals Unit
• CAES ADC
• Gaisler FaultTolerantMemoryController
• LPC USART
• MiV CoreUART
• NXP LPUART
• RenesasDA Watchdog
• RenesasDA14 ClockGenerationController
• RISC-V Platform Level Interrupt Controller
• STM32 DMA
• ZynqMP IPI
• ZynqMP Platform Management Unit

For installation instructions, see the README.

Added and improved architecture support:

• support for Core-Local Interrupt Controller (CLIC) in RISC-V, enabling several flavors of the (not yet ratified) RISC-V Fast Interrupts specification
• various improvements to x86 architecture support, including virtual address translation fixes
• RISC-V custom instructions now have to follow length encoding patterns, as specified in the ISA manual (section 1.2 Instruction Length Encoding)
• fixed fetching RISC-V instruction with PMP boundary set exactly after the instruction
• fixed setting MPP after mret on RISC-V platforms without user privilege level
• fixed RISC-V PMPCFG CSR operations not respecting the write any, read legal semantics
• fixed RISC-V fcvt.wu.s, fcvt.lu.s and vmulh.vv instructions implementation

Added and improved platform descriptions:

• NPCX9 platform with improved bootrom implementation
• Chip revision tags in the Renesas DA14592 platform
• Fixed MPU regions configuration in Cortex-R8 SMP platform description
• Nuvoton NPCX9M6F EVB
• Microchip Mi-V, with correct Privileged Architecture version

Added peripheral models:

• MAX32655 UART
• NEORV32 Machine System Timer
• NEORV32 UART
• KB1200 UART
• RISC-V Core-Local Interrupt Controller
• STM32WBA CRC
• VeeR EL2 RISC-V core with custom CSRs

Added demos and tests:

• HiRTOS sample running on a dual-core Cortex-R52
• Xen hypervisor running on Cortex-R52 with Zephyr payload
• remoteproc demo on ZynqMP, with Linux running on Cortex-A loading Zephyr to Cortex-R
• NPCX9 Zephyr-based tests for GPIO and I2C
• synthetic tests for RISC-V Core-Local Interrupt Controller
• RISC-V Core-Local Interrupt Controller tests based on riscv-arch-test
• Zephyr bluetooth HR demo running on 4 nRF52840 in host / controller split communicating with HCI UART
• Zephyr running hello_world sample on X86
• regression test for custom RISC-V instructions not following the length encoding pattern

Added features:

• CPU cache analysis tool using the ExecutionTracer interface
• initial GPIO support via External Control API
• Wait For Lines On Uart keyword for Robot Framework for multiline matching
• ability to specify aliases for names of constructor parameters in REPL, simplifying adaptation to API changes
• ability to specify implemented privilege levels on RISC-V processors
• initial SMC handling for ARMv8 CPUs
• ability to load snapshots (.save files) from CLI
• mechanism for enabling sysbus transaction translations for unimplemented widths in runtime
• network based logging backend
• option to assert match on the next line in UART keywords for Robot Framework
• remapping exception vector in Arm CPUs having neither VBAR nor VTOR
• support for declaring clusters of cores in REPL files
• support for loading gzip compressed emulation snapshots
• NetMQ and AsyncIO integration

Changed:

• ExecutionTracer logs additional physical address on memory access when MMU translation is involved
• ExecutionTracer tracks values written to/read from memory if TrackMemoryAccesses parameter is used
• added the ability to override build properties
• added the ability to track memory accesses when address translation is active
• External Control client `run_for` example can now progress time multiple times without reconnecting
• machine by default disallows spawning a GdbServer with CPUs belonging to different architectures.
• made user-configured $CC the default value for Compiler and LinkerPath and $AR for ArPath
• paths encapsulated in quotes can handle names with whitespaces
• paths in Monitor can be encapsulated in quotes in more contexts
• improved precision of timer reconfiguration
• translation library will attempt to expand its code buffer when running out of space
• improved flexibility of parameter passing to registration points in REPL, as used by GIC
• improved flexibility of the logLevel command
• improved Renode pausing responsiveness when using TAP interface on Linux
• improved performance of External Control API renode_run_for function
• simplified per-core registration API in REPL files
• renamed ``PrivilegeArchitecture`` to ``PrivilegedArchitecture`` on RISC-V
• unified STM32 CRC peripherals so they use a single class configured with the STM32Series enum
• co-simulated peripherals protocol on writes directed to system bus
• MacOS now uses ``mono`` instead of ``mono64`` as a runner, which is equivalent since Mono 5.2
• time updates are now deferred when possible to improve performance
• virtual time precision is now 1 nanosecond instead of 1 microsecond
• limited unnecessary invalidations of memory for multicore platforms
• CPU-specific peripheral registrations have now higher priority than the global ones
• undefined AArch64 ID registers are now treated as RAZ

Fixed:

• initialization of VFP registers for Armv8 CPUs
• support for building tlibs with clang
• interruption of instructions block on precise pause
• accessing RISC-V counter CSRs for lower privilege levels for privileged specification 1.10 and newer
• Time Framework errors when handling halted CPUs
• running renode and renode-test commands via symlinks
• serialization of ARMv8-A CPUs
• serialization of some complex classes
• listing of registration points for peripherals registered at both cpu and sysbus
• handling of watchpoints set at addresses above the 32-bit range
• crashes when using both aliased attribute name and normal name at the same time
• possible hang when disabling logging of peripheral accesses
• handling of exclusive store/load instructions for ARMv7-R CPUs
• handling of interrupting execution in GDB on multicore platforms in all-stop mode
• allocating huge amount of memory for translation cache on CPU deserialization
• invalid undefined instruction faults for Armv8 CPUs
• GDB getting confused when receiving Ctrl-C on multicore platforms
• LSM303 peripheral test
• CS7034 "specified version string does not conform to recommended format" warning appearing when building
• Vegaboard-RI5CY demo failing to boot
• exception thrown on an empty message in log when failing a Robot test
• linking and imports in the External Control library
• nonstandard configuration byte when disabling Telnet line mode
• printing skipped test status
• version information not appearing correctly after running `renode --help`

Improvements in peripherals:

• Ambiq Apollo4 System Timer
• Arm Generic Interrupt Controller
• ARM Generic Timer
• Arm Performance Monitoring Unit
• Arm Snoop Control Unit
• Arm CPUs
• Arm Signal Unit
• Gaisler APB UART
• K6xF Multipurpose Clock Generator
• KB1200 UART
• LPC USART
• Macronix MX25R
• MAX32650 WDT
• Mi-V Core Timer
• MPFS SD controller
• NEORV32 UART
• NPCX MDMA
• NPCX ITIM, including both 32 and 64-bit flavors of the peripheral
• NPCX TWD
• NPCX SMBus
• NPCX UART
• nRF52840 CLOCK
• NVIC
• Renesas RA6M5 SCI
• RCAR UART
• SAMD20 UART
• SD card
• STM32 UART
• STM32 LTDC
• STM32 CRC
• STM32 Timer
• STM32F4 Flash with added mass erase and sector erase commands
• STM32L0 RCC model with added support for Low-power timer (LPTIM) reset
• STM32WBA GPDMA
• SynopsysDWCEthernetQualityOfService incorrectly resetting transmit/receive buffer position when suspending its DMA engine
• VirtIO
• Zynq7000 System Level Control Registers

For installation instructions, see the README.

Added and improved architecture support:

• improved support for SMP processing in Armv8 and Armv7
• configuration signals for Arm cores
• LOB extension (without tp variants) for Armv7
• VSTRW instruction support from Armv8.1-M MVE
• support for additional Arm CP14 and CP15 registers
• Armv8 LDM (user) instruction will update registers predictably even when executing in System Mode, instead of being UNPREDICTABLE according to Arm documentation
• basic support for Cortex-A5 CPU type
• DCIMALL instruction for Aarch32 CPUs
• IMP_CDBGDCI instruction for Cortex-R52 CPUs

Added and improved platform descriptions:

• timer interrupts configuration for STM32F4-based platforms

• improvements to networking configuration for StarFive JH7100

• improvements to Renesas R7FA2E1A9, R7FA2L1A, R7FA4M1A, R7FA6M5B, R7FA8M1A SoC

• improvements to UT32M0R500 SoC

• platform with example sensor connections for CK-RA6M5

• multicore Cortex-R52 platform

• multicore Cortex-A53 with GICv3 in SMP configuration

• improvements to the Cortex-R52 platform

• GIC architecture version selection for many Arm platforms

• added Arm signal unit support for Cortex-R8 and multicore Cortex-R8 platforms

• merged Zynq Ultrascale+ into a single platform with both Cortex-A and Cortex-R CPUs

• updated peripherals registration for STM32F0, STM32F4, STM32F746, STM32G0, STM32H743, STM32L071, STM32L151, STM32L552, STM32WBA52 SoCs

• Renesas CK-RA6M5 board

• Beagle-V Fire, with Microchip's PolarFire SoC

Added peripheral models:

• Gaisler ADC
• NPCX GPIO
• NPCX SMBus
• NXP OS Timer
• Renesas DA SPI
• Renesas RA IIC
• Renesas DA14 GeneralRegisters
• Renesas DA14 XTAL32MRegisters
• S32K3XX EMAC
• S32K3XX FlexCAN
• S32K3XX FlexIO with SENT and UART endpoints
• S32K3XX GMAC
• S32K3XX Low Power IIC
• STM32H7 Crypto Accelerator
• STM32H7 QuadSPI
• STM32WBA GP DMA
• UT32 CAN
• VirtIO Filesystem device
• ZynqMP Inter Processor Interrupt controller
• ZynqMP Platform Management Unit
• ZMOD4410 and ZMOD4510 air quality sensors
• AK09916 and AK09918 3-axis electronic compass sensors
• generic configurable Pulse Generator block

Added demos and tests:

• I2C echo test for Renesas DA14592
• addtional unit tests for CRCEngine
• I2C mode tests for Renesas RA8M1 SCI
• BeagleV-StarLight ethernet tests
• serialization tests for Armv8-A and Armv8-R cores
• Cortex-R8 Zephyr tests
• configuration signals tests for Cortex-R8
• NXP S32K388 Low Power SPI test
• HiRTOS samples (including multicore) on Cortex-R52
• Renesas RA6M5 platform tests including SCI SPI, ICM20948, HS3001, IIC
• EXT2 filesystem Zephyr tests based on SiFive FU740
• STM32H7 Nucleo test for CRYPTO and SPI
• tests for GDB accessing peripheral space
• regression tests for ARMv8 Security State and Exception Level after core initialization
• VirtIO Filesystem directory sharing test
• Zephyr SMP test for Cortex-R52
• aws_cc test for the Renesas CK-RA6M5 board
• machine log level test
• range locking tests in sysbus.robot

Added features:

• mechanism for integrating Renode with SystemC simulations
• VirtIO-based directory sharing with host OS
• new GIC redistributor regions registration methods for multi-core platforms
• CAN analyzer support in Wireshark integration
• CPU-specific function names lookup support
• ability to clear CPU-specific or global function names lookups
• SENT protocol support
• LIN protocol support
• IADC interface for generic ADC control
• support for specifying additional offset to function names addresses in lookups
• locking sysbus accesses to specified ranges
• easier access to externals in Python scripts via externals variable
• external control API with C client library
• integration with dts2repl tool
• virtual CAN host integration via SocketCAN bridge
• ability to control log level of the whole machine with the logLevel command
• ability to specify Privileged Architecture Version 1.12 on RISC-V processors
• optional CPU context in locking sysbus accesses to peripherals

Fixed:

• Migrant not keeping track of all child-parent connections in the Reflection mode
• Arm PMSAv8 configuration using stale values in some circumstances
• Armv7 CP15 registers - ADFSR, AIFSR, non-MP BP*, DC* and IC* registers
• Armv7 and older memory barrier instructions and CP15 registers (DMB, DSB and DWB)
• read accesses to write-only Aarch32 coprocessor registers
• Armv7/Armv8 MPIDR register
• breakpoints serialization and deserialization
• calculation of target EL and interrupt masking for Armv8 Aarch32
• crashes in certian register configurations for Armv8 Aarch32
• FIQs being disabled with no way of enabling them for GICv3 and onwards
• NA4 range end address calculation in RISC-V PMP
• effective PMP configuration calculation in RISC-V when mstatus.MPRV is set
• RISC-V vector load and store segment instructions
• crashes when a breakpoint and a watchpoint trigger at the same instruction
• RISC-V PMP NAPOT grain check implementation
• TranslationCPU's CyclesPerInstruction changes during runtime not being automatically applied to ArmPerformanceMonitoringUnit's cycle counters
• unmapping of memory segments
• unregistering peripherals
• valid Ethernet frames sometimes getting rejected due to CRC mismatch
• virtual time advancing too far when pausing the emulation
• CCSIDR for L1 data cache in Arm Cortex-R8
• CCSIDR for L2 cache in Arm Cortex-R5/R8
• renode-test --include behavior for NUnit test suites
• atomic instructions handling when running multithreaded program on a single CPU machine
• automatic 64-bit access translations on system bus
• crashes on Cortex-M construction if NVIC is already attached to a different core
• exclusive load/store instructions on Armv8
• failures in monitor-tests.Should Pause Renode under certain conditions
• invalid Asciinema generation if the UART output contains a backslash character
• logging value written on an unhandled tag write
• names of Arm TCM registers
• pausing on SemihostingUart events in Xtensa CPUs
• reporting thread ID as decimal number in GDB's query command - cpuId restricted to 32
• selecting PMP access mode for RISC-V cores
• serialization for Armv8-A and Armv8-R cores
• suppressed SP and PC initialization on halted Cortex-M cores
• cache selection in Armv7 and older CPUs, now verified with CLIDR when reading CCSIDR
• precise pausing causing parts of the instruction to be executed twice
• ARM MPU ignoring memory restriction check to the page that was previously accessed even if region/subregion permissions don't match
• Armv8-R AArch32 executing in Secure State instead on Non-Secure
• Armv8-R changing Security State, while it should never do so
• Armv8 cores not propagating their Exception Level and Security State outside tlib correctly after creation
• DMAEngine memory transactions with when not incrementing source or destination addresses
• RISC-V BEXT instruction handling
• RISC-V xRET instructions not changing status bits correctly
• SocketServerProvider not closing correctly without any connected clients
• detection of test failures which should be retried when renode-test's --retry option is used
• handling peripheral accesses when debugging with GDB
• initialization of PC and SP on leaving reset on Cortex-M
• printing of possible values for invalid Enum arguments in Monitor commands
• heterogeneous platforms handling in GDB
• single step execution mode in Xtensa cores
• variable expansion in Monitor

Changed:

• Terminal Tester delayed typing now relies on virtual time
• removed AdvancedLoggerViewer plugin
• improved TAP networking performance on Linux
• reduced overhead of calling tlib exports
• TranslationCPU's CyclesPerInstruction now accepts non-integer values
• CPU Step call now automatically starts the emulation
• upgraded Robot Framework to 6.1, to work with Python 3.12
• renamed the ID property of Arm cores to ModelID
• improved Arm core performance
• improved logging performance if lower log levels are not enabled
• added host memory barrier generation to TCG
• actions delayed with machine.ScheduleAction can now execute as soon as the end of the current instructions block (it used to be quantum)
• CPU's SingleStepBlocking and SingleStepNonBlocking ExecutionModes were replaced by SingleStep and emulation.SingleStepBlocking was added
• blockOnStep was removed from StartGdbServer
• single-step-based tests were refactored due to automatic start on Step and ExecutionMode changes

Improvements in peripherals:

• Andes AndeStarV5Extension.cs - Added Configuration and Crash Debug CSRs
• Arm Generic Interrupt Controller, with changes to v1, v2 and v3 versions, focused on improving multicore support for both Armv7 and Armv8 platforms
• Gaisler APBUART
• Gaisler GPTimer
• Gaisler Ethernet
• Gaisler MIC
• Kinetis LPUART
• NPCX FIU
• NPCX Flash
• NXP LPSPI
• Renesas RA8M1 SCI
• Renesas DA I2C
• Renesas DA Watchdog
• Renesas DA14 DMA
• Renesas RA6M5 SCI
• Renesas DA DMABase
• S32K3XX LowPowerInterIntegratedCircuit
• SDCard
• STM32 PWR
• STM32F4 CRC
• STM32H7 RCC
• Synopsys DWCEthernetQualityOfService
• Synopsys EthernetMAC
• VirtIOBlockDevice, now based on VirtIO MMIO version v1.2
• Xilinx IPI mailbox
• BME280 sensor
• ICM20948 sensor
• SHT45 sensor

For installation instructions, see the README.

Added architecture support:

• initial support for ARMv7-R and Cortex-R8, verified with ThreadX and Zephyr
• initial support for Cortex-A55
• initial support for Cortex-M23 and Cortex-M85
• support for RISC-V Bit Manipulation extensions - Zba, Zbb, Zbc and Zbs
• support for RISC-V Half-precision Floating Point (Zfh) extension, including vector operations
• support for RISC-V Andes AndeStar V5 ISA extension

Added and improved platform descriptions:

• generic Cortex-R8 platform
• Renesas EK-RA2E1 board with R7FA2E1A9 SoC
• Arduino Uno R4 Minima platform with Renesas F7FA4M1A SoC
• Renesas CK-RA6M5 board with R7FA6M5B SoC, with initial radio support
• Renesas EK-RA8M1 board with R7FA8M1A SoC
• Renesas R7FA2L1A SoC
• Renesas DA14592 SoC
• Renesas RZ/T2M-RSK board with RZ/T2M SoC
• Gaisler GR712RC SoC with UART, timer, GPIO, FTMC and Ethernet
• Gaisler GR716 SoC with UART, timer and GPIO
• Gaisler UT32M0R500 SoC with UART, timer and GPIO
• NXP S32K388 with UART, timers, watchdog, SIUL2, SPI, Mode entry module and others
• NXP LPC2294 SoC with UART, CAN, timer and interrupts support
• Xilinx Zynq UltraScale+ MPSoC platform support with single core Cortex-A53, UART, GPIO and I2C
• singlecore Cortex-R5 part of Zynq UltraScale+ MPSoC platform with UART, TTC, Ethernet and GPIO
• Nuvoton NPCX9 platform support with UART, various timers, SPI, flash and other peripherals
• ST Nucleo H753ZI with STM32H753 SoC with a range of ST peripherals
• updates to Armv8-A platforms
• updates to Ambiq Apollo4
• updates to Xilinx Zynq 7000
• various updates in STM32 platform files

Added peripheral models:

• ABRTCMC, I2C-based RTC
• Altera JTAG UART
• Ambiq Apollo4 Watchdog
• Arm Global Timer
• Arm Private Timer
• Arm SP804 Timer
• ArmSnoopControlUnit
• BCM2711 AUX UART
• BME280 sensor
• Betrusted EC I2C
• Betrusted SoC I2C
• Bosch M_CAN
• CAN to UART converter
• Cadence Watchdog Timer
• Gaisler APBUART
• Gaisler GPIO
• GigaDevice GD32 UART
• HS3001 sensor
• ICM20948 sensor
• ICP10101 sensor
• Infineon SCB UART
• LINFlexD UART
• MB85RC1MT Ferroelectric Random Access Memory
• MXIC MX66UM1G45G flash
• NPCX FIU
• NPCX Flash
• NPCX HFCG
• NPCX ITIM32
• NPCX LFCG
• NPCX MDMA
• NPCX Monotonic Counter
• NPCX SPIP
• NPCX Timer and Watchdog
• NPCX UART
• NXP LPC CAN
• NXP LPC CTimer
• NXP LPC USART
• OB1203A sensor
• PL190 vectored interrupt controller
• PL330_DMA (CoreLink DMA-330) Controller
• Renesas DA14 DMA peripheral
• Renesas DA14 GPIO
• Renesas DA14 General Purpose Timer
• Renesas DA14 UART
• Renesas DA14 I2C
• Renesas DA16200 Wi-Fi module
• Renesas RA series AGT
• Renesas RA series GPIO
• Renesas RA series GPT
• Renesas RA series ICU
• Renesas RA series SCI
• Renesas RZ/T2M GPIO
• Renesas RZ/T2M SCI
• S32K3XX Miscellaneous System Control Module
• S32K3XX Periodic Interrupt Timer
• S32K3XX Real Time Clock
• S32K3XX Software Watchdog Timer
• S32K3XX System Integration Unit Lite 2
• S32K3XX System Timer Module
• S32K3XX FlexIO stub
• S32K3XX Mode Entry Module
• SHT45 temperature/humidity sensor
• SPI NAND flash
• STM32WBA PWR
• Samsung K9 NAND Flash
• Smartbond UART
• Universal Flash Storage (JESD220F)
• Universal Flash Storage Host Controller (JESD223E)
• XMC4XXX UART
• ZMOD4xxx sensor
• Zynq 7000 System Level Control Registers

For installation instructions, see the README.

Added architecture support:

• initial support for ARMv8-A, verified with a range of software, from Coreboot and U-Boot to Linux
• initial support for ARMv8-R, verified with U-Boot and Zephyr

Added and improved platform descriptions:

• generic Cortex-A53 platform, in flavors with GICv3 and GICv2
• generic Cortex-A78 platform
• generic Cortex-R52 platform
• HiFive Unmatched platform support, with UART, PWM, I2C, GPIO, Ethernet, QSPI and other peripherals
• Nucleo WBA52CG with STM32WBA52
• updated OpenTitan and EarlGrey platform to a newer version
• various updates in STM32 platform files
• translation support for Espressif ESP32 chips

Added peripheral models:

• ARM GIC, compatible with various specification versions
• ARM generic timer
• CMSDK APB UART
• Cypress S25H Flash
• EFR32xG2 I2C
• EFR32xG2 RTCC
• EFR32xG2 UART
• Marvell Armada Timer
• MXC UART
• OMAP Timer
• OpenTitan Entropy Distribution Network
• Quectel BC66
• Quectel BG96
• SI7210 Temperature
• SPI multiplexer
• STM32F4 CRC
• STM32F4 Flash
• STM32H7 Flash
• STM32WBA Flash
• STM32H7 Hardware Semaphore
• STM32H7 SPI
• STM32WBA SPI
• STM32WBA ADC
• Synopsys DWC Ethernet QoS model, along with Linux-based tests
• TMP108 Temperature sensor

Added demos and tests:

• Cortex-A53 and Cortex-A78 running Coreboot, ATF and Linux
• Zephyr running echo_client demo on STM32F7-disco with Quectel BG96
• basic Cortex-A53 Zephyr hello-world test and sample
• additional Zephyr tests for Cortex-A53: synchronization, philosophers, kernel FPU sharing
• seL4 Adder Sample test for Cortex-A53
• range of Zephyr tests for Cortex-R52, along with custom-made, synthetic tests
• precise pausing tests for LED and terminal tester

Added features:

• renode-test allows to run tests with a specified tag via the --include switch
• DPI interface for external HDL simulators, supporting AXI4 interface
• portable package creation on dotnet
• option to have Robot test pause execution deterministically after a match in various testers: UART, LED, log
• duty cycle detection in LED tester
• option to load files (e.g. raw binaries, hex files) to different localizations, like memories
• support for relative paths in REPL file using directive
• MPU support for Cortex-M
• FAULTMASK register in Cortex-M
• support for Trace Based Model performance simulator by Google
• read and write hooks for peripherals
• DPI interface support for co-simulating with RTL, with initial support for AXI4 bus
• build.sh --profile-build switch to enable easier profiling of translation libraries
• mechanism for progressing virtual time without executing instructions
• support for subregions in Cortex-M MPU
• support for FPU exceptions for Cortex-M
• quad word (64-bit) peripherals API
• CSV2RESD tool, for easy generation of RESD files
• automatic selection of port used to communicate between Renode and Robot
• option to pause emulation of Robot keywords
• support for NMI interrupts in RISC-V
• option to save Renode logs for all tests
• Execute Python keyword in Robot tests

Changed:

• GDB interacts with Renode much faster
• Renode now uses Robot Framework 6.0.2 for testing (with an option to use other versions at your own risk)
• RESD format now accepts negative sampleOffsetTime
• HEX files loader now supports extended segment address and start segment address sections
• GDB autostart parameter now starts the simulation as soon as the debugger is connected
• VerilatorIntegrationLibrary is now part of Renode packages
• improved performance of the virtual time handling loop
• improved parsing of RESD files
• improved memory allocation mechanism to allocate memory regions larger than 2GiB
• support for mapping memories on very high offsets
• improved GDB connection robustness
• exposed Monitor as a variable in Python hooks
• improved the GDB compare helper script
• improved handling of input files in TFTP server module

Fixed:

• cursor blinking in terminal on Windows
• crash when NetworkServer tried to log an invalid packet
• race condition when trying to pause during the machine startup
• platform serialization when CPU profiler is enabled
• limit buffer behavior in verilated peripherals when they are reset
• registration is no longer taken into account when looking for dependency cycles in REPL files
• exception when issuing a DMA transaction during register access
• reported PC on exception when executing vector instructions in RISC-V
• several RISC-V vector instructions handling, e.g. vfredosum, vsetivli and vector_fpu
• invalid instruction block exiting on RISC-V
• handling of c.ebreak instruction in RISC-V, allowing for software breakpoints
• building fixes on dotnet
• removing of IO access flag from memory pages
• invalidation of dirty translation blocks
• handling of MMU faults on address translations
• serialization of RESD files
• automatic creation of TAP interface on Linux
• ARM LDA/STL instructions decoding
• handling of platforms containing both 32- and 64-bit CPUs
• file permissions in .NET portable packages
• handling of non-resettable register fields
• several RISC-V vector instructions
• handling of the context menu in the Monitor window
• support for Cortex-M4F in LLVMDisassembler
• packets matching method in NetworkInterfaceTester
• address calculations in DMA engine
• custom build properties handling in Renode build script
• handling of time reporting and empty test cases in renode-test

Improvements in peripherals:

• AmbiqApollo4 Timer
• ArrayMemory
• AS6221 Temperature sensor
• AT Command Modem
• AT91 Timer
• Cadence UART
• Cortex-M Systick
• EF32MG12 LDMA
• Ibex
• LIS2DW12 Accelerometer
• LiteX I2C
• LSM6DSO
• MAX30208 Temperature sensor
• MAX32650 GPIO
• MAX32650 I2C
• MAX32650 RTC
• MAX32650 SPI
• MAX32650 Timer
• MAX32650 TPU
• MAX32650 WDT
• MAX86171 AFE
• nRF52840 SPI
• nRF52840 I2C
• nRF52840 GPIO
• OpenTitan HMAC
• OpenTitan PLIC
• OpenTitan ROM
• OpenTitan OTP
• OpenTitan Key Manager
• OpenTitan Flash
• OpenTitan Reset Manager
• OpenTitan KMAC
• OpenTitan CSRNG
• OpenTitan Alert Handler
• OpenTitan Timer
• OpenTitan OTBN
• PL011 UART
• Quectel BC660K
• SAMD5 UART
• SiFive GPIO
• Silencer
• STM32 DMA
• STM32G0 DMA
• STM32 EXTI, with specific implementations for STM32F4, STM32H7 and STM32WBA
• STM32 GPIO
• STM32F7 I2C
• STM32L0 LPTimer
• STM32L0 RCC
• STM32H7 RCC
• STM32F4 RTC
• STM32 SPI
• STM32 Timer
• STM32F7 USART

For installation instructions, see the README.

Added and improved platform descriptions:

• basic Adafruit ItsyBitsy M4 Express platform with UART and memories
• various STM32 platforms with improved EXTI connections, IWDG configuration, and new CRC, Flash, PWR, RCC, and LPTimer models added to selected platforms
• MAX32650 with a new I2C model
• Zynq 7000 with new I2C, SPI, UART and TTC models
• Apollo 4 with a new Timer model and a program_main2 bootrom function mock
• OpenTitan Earlgrey with new OTBN accelerator, AON Timer, System Reset controller, Entropy source, and SRAM controller models
• nRF52840 with a new EGU model
• EFR32MG1x with a new LDMA model and improved USART interrupt connections

Added peripheral models:

• Apollo4 IOMaster I2C mode
• Apollo4 Timer
• AS6221 skin temperature sensor
• Cadence I2C controller
• Cadence SPI controller
• Cadence TTC
• Cadence UART
• Cadence xSPI controller
• EFR32MG12 LDMA controller
• LIS2DW12 accelerometer sensor
• LC709205F Fuel Gauge
• Macronix MX25R flash
• MAX30208 temperature sensor
• MAX32650 I2C controller
• MAX77818 Fuel Gauge
• MAX86171 Optical AFE
• NRF52840 EGU
• OpenTitan AON Timer
• OpenTitan Big Number Accelerator (OTBN) full model
• OpenTitan ClockManager stub
• OpenTitan Entropy Source controller
• OpenTitan SRAM controller
• OpenTitan SystemReset controller
• Quectel BC660K radio
• RV8803 RTC
• STM32F0 CRC
• STM32H7 RCC
• STM32L0 Flash controller
• STM32L0 Low Power Timer
• STM32L0 PWR
• TMP103 temperature sensor

Added demos and tests:

• RTC mode unit test
• Adafruit ItsyBitsy M4 Express Zephyr shell_module test
• STM32L072 tests for: DMA, PVD interrupt, SPI flash, IWDG, LPUART, EEPROM, and CRC
• STM32F4 tests for RTC and running an STM32CubeMX app
• Zynq tests for I2C, TTC, SPI flash, xSPI, and UART based on Linux

Added features:

• support for RESD - Renode Sensor Data format, allowing users to provide multiple sensors with time-coordinated data specific for a given sensor; currently supported in MAX86171, MAX30208, AS6221, and LSM6DSO
• reorganized CPU classes and interfaces, allowing for easier integration of external CPU simulators
• IOMMU, with example usage in WindowIOMMU, WindowMMUBusController, and SimpleDMA
• new key bindings in the Monitor: Ctrl+D for closing the window and Ctrl+U for clearing the current input
• new key bindings in all terminal windows: Shift+Up/Down arrow for line scrolling and Shift+Home/End for jumping to the beginning and the end of the buffer
• option to configure UART window location offsets via the config file
• support for 64-bit bus accesses and 64-bit peripherals
• support non-resettable peripheral registers and register fields
• option to register hooks to be called whenever a RISC-V register is accessed - this can be used to emulate non-standard implementation of these registers
• option to set CPU exceptions from the outside of the CPU
• Robot keyword to verify that GPIO has a specified state for a given period of time
• verbose mode in Robot tests

Changed:

• Robot tests do not need a header with settings and keywords anymore
• changed the conditional syntax in Robot tests to use IF/ELSE for compatibility with newer Robot Framework versions
• cleaned up tests-related file organization in the repository
• simplified flags for renode-test under dotnet
• added skip_mono and skip_dotnet tags to Robot tests
• removed internal signal mappings from STM32 EXTI, making the interrupt routing more explicit in REPL files
• console mode will be started instead of telnet when the UI fails to start
• reset can now be executed on a not started machine
• expanded the Execution Tracer with TrackMemoryAccesses and TrackVectorConfiguration options, along with disassembler-generated info
• OnMemoryAccess hooks now receive the current PC as a parameter
• changed the CRCEngine API and improved implementation
• ELF symbol lookup will now skip several types of unimportant symbols
• tags can now have zero width to ease the creation of variable width registers
• added option to invert reset logic in AXI4Lite
• added handling of the WSTRB signal in AXI4Lite
• added support for various address lines connections in Wishbone
• added various access lengths support for verilated peripherals
• timeout value for Verilator connections can now be defined in compile time
• all architectures now sync their PC on memory accesses
• UARTBase is now a container for IUART devices
• added option to clear all event subscribers in LimitTimer
• added ITimer interface for handling basic timer properties
• extended the excluded assembly list in TypeManager to speed up startup on dotnet

Fixed:

• flushing of the log when using the lastLog command
• deadlock when using the --console mode on dotnet with collapsed log entries enabled
• Wireshark handling on macOS
• TAP support on macOS
• Asciinema usage in multi-machine setups
• closing of Renode in several problematic scenarios
• handling of end of file detection in HEX parsing
• robustness of BLESniffer
• timestamps discrepancies in file logs and console logs
• compilation under Visual Studio on Windows
• compilation on Windows when the PLATFORM environment variable is set
• graph titles for metrics visualizer
• handling of peripheral regions in Profiles
• file sharing and access type settings for open files
• floating point registers access on RV32
• several RISC-V Vector instructions
• crash when the CPU is created with an invalid type
• RISC-V PMP config reading and writing and NAPOT decoding
• translation cache invalidation in multicore RISC-V scenarios
• SEV generation on Cortex-M
• handling of multi-instructions blocks in Xtensa
• execution of too many instructions in a single block
• button sample tests for STM32F072q
• fastvdma co-simulation test
• qCRC packet handling in GDB
• decoding of GDB packets, selecting the command handler based on the longest match for a packet
• address translation in GDB
• UARTToSpiConverter logic and user experience
• handling of Step parameter in ClockEntry
• changing of frequency for divider calculation in ComparingTimer
• cleanup of old clock entries

Improvements in peripherals:

• AmbiqApollo4 IOMaster
• AmbiqApollo4 RTC
• AthenaX5200
• Cadence TTC
• Dummy I2C Slave
• EFR32 CMU
• EFR32 USART
• EFR32 RTCC
• Generic SPI Flash
• HiMax HM01B0
• I2C dummy device
• LSM6DSO IMU
• Mapped Memory
• Micron MT25Q
• MPFS PDMA
• NRF52840 SPI
• NRF52840 I2C
• NRF52840 RTC
• NVIC interrupt controller
• OpenCores I2C
• OpenTitan I2C
• OpenTitan Flash controller
• OpenTitan LifeCycle controller
• OpenTitan ROM controller
• SAMD5 UART
• SI70xx temperature sensor
• SiFive GPIO
• STM32 GPIO
• STM32 SPI
• STM32 Timer
• STM32F4 IndependentWatchdog
• STM32F4 RTC
• STM32F7 I2C
• STM32F7 USART
• STM32L0 RCC
• STM32G0 DMA

For installation instructions, see the README.

Added platforms:

• Ambiq Apollo4 with ADC, GPIO, IO Master, System Timer, RTC, UART and other peripherals
• STM32L07x with ADC, GPIO, I2C ,RTC, SPI, Timer, USART, IWDG, DMA and other peripherals (RCC)
• verilated Ibex core with the rest of the platform natively in Renode

Added models:

• MAX32650 TPU with CRC32 support
• basic support for MAX32650 ADC
• MAX32650 SPI
• MAX32650 Watchdog
• LSM6DSO IMU
• EFR32xG12DeviceInformation
• External CPU stub as a base for integration of other CPU simulators
• OpenTitan SPI host
• OpenTitan I2C host
• OpenTitan Alert Handler, along with updates to other OpenTitan peripherals with alert functionality
• new algorithms and cores in AthenaX5200
• EFR32MG1 BitAccess
• i.MX RT GPTimer

Added demos and tests:

• STM32L072 Zephyr shell_module demo and test
• Ambiq Apollo4 Hello World example from Ambiq Suite and various peripheral tests
• MAX32652 EVKIT Hello World example from MAX32652 SDK
• FPGA ISP co-simulation demo and test

Added features:

• experimental support for .NET 6 framework
• guest-application profiling for ARM
• Interrupt hooks for ARM
• BLE sniffer support for Wireshark
• Perfetto profiler format support in guest-application profiling, along with process detection on RISC-V
• binary output format of execution tracer, along with a Python helper script to decode data
• new Run Until Breakpoint keyword for Robot tests
• verbose mode in Robot tester
• region of interest support in FrameBufferTester
• framework for providing timestamped sensor data
• WishboneInitiator bus in Verilator support
• nightly “sources” package with the whole content required for building Renode offline

Organizational improvements:

• added GitHub issue and PR templates, along with an issue reproduction repository
  updated contributing instructions

Changed:

• added mapping for l2ZeroDevice in PolarFire SoC
• added caching of canvas bounds in TermSharp for improved performance
• restructured height map storage in TermSharp
• updated descriptions of SLTB004A and EFR32MG12 targets
• restructured CPU-related class hierarchy
• disabled TCG optimizations and liveness analysis for improved performance
• updated OpenTitan supported version, changing a range of OpenTitan peripherals
• major refactor of VerilatorIntegrationLibrary, with new interfaces and code restructuration
• updated symbol exclusion rules not to include $x symbol names in SymbolLookup
• disabled TLB flushing in RISC-V on mode change for improved performance
• allowed more than one page permission at a time in RISC-V, reducing the number of address translations
• improved output of Robot tests with timestamps and explicit test results after each suite
• SD card controller now supports more card types

Fixed:

• PMP implementation for RISC-V
• several RISC-V vector instructions including floating-point vector instructions
• 'Take Screenshot' button in VideoAnalyzer
• non-blocking CPU stepping
• crash when loading file without sufficient permissions
• external MMU not respecting the no_page_fault flag
• issues with concurrent creation of config file
• indeterminism of sel4_extensions test
• GDB Stub not issuing an error when trying to add zero-sized watchpoint
• handling of watchpoints on big-endian platforms
• portability of MSBuild calls across different host systems
• PolarFire SoC Watchdog test
• serialization of FrameBufferTester
• translation cache flushing after reset

Improvements in peripherals:

• Cortex-M NVIC
• HPSHostController
• NRF52840 Watchdog
• BMC050 accelerometer
• MAX32650 RTC
• MAX32650 GCR
• STM32F7 I2C
• STM32G0 DMA
• Micron MT25Q
• i.MX RT GPIO

For installation instructions, see the README.

Added platforms:

• MAX32652 with UART, GPIO, Timer, PWRSEQ, GCR and RTC
• Thunderboard Sense 2 (SLTB004A) based on EFR32MG12

Added models:

• STM32G0 DMA controller
• OpenTitan CSRNG
• OpenTitan OTP controller
• OpenTitan Life Cycle controller
• USBserialport_S3B model for Qomu
• SAMD5 UART
• SAMD20 UART
• AES and Message Authentication cores for AthenaX5200
• LiteX MMCM controller in the 32-bit CSR width configuration
• LiteX Framebuffer in the 32-bit CSR width configuration

Added demos:

• Qomu running Zephyr shell
• SLTB004A running Gecko SDK baremetal CLI sample

Added features:

• guest-application profiling support
• TAP integration on Windows
• interrupt end hooks for RV64
• option for gathering execution metrics when running tests
• tests for logging from a sub-object
• PolarFireSoC Watchdog tests
• the disassembly output format to the Execution Tracer module
• option for filtering messages by log level in the log tester

Changed:

• improved support for ARMv8-M registers
• added option to compare raw values of selected registers in the gdb_compare script
• implemented generation of guest-host PC mappings info on block translation
• added Frequency property to ComparingTimer
• monitor-tests: Use virtual time in the pause test
• added static flushing to the logger
• included missing tools (like gdb_compare, sel4_extensions) in all packages
• added precompilation of Python scripts before running (to detect errors early)
• added user-specified file paths handling
• added filtering of ANSI escape codes from Robot tests keyword results
• added option to enable profiler globally in EmulationManager
• added command to disable automatic symbol switching in seL4 GDB extensions
• improved RISC-V kernel breakpoints support in seL4 GDB extensions
• code generator is now compiled with more aggressive optimizations
• changed the CPU class structure, allowing for core implementations not based on translation libraries
• updated the Nexys Video platform description and demo binaries

Fixed:

• 'Should Output Voice Data' test for QuickFeather
• various RISC-V vector instructions
• register values accessing in RISC-V
• help button behavior in AdvancedLoggerViewer
• concurrent access to Pixel Manipulation Tools
• clock residuum handling, e.g. improving the behavior of the BLE demo
• serialization of externals and GDB stub
• stacktrace reporting when exception is rethrown on the native-managed boundary
• packaging of license files from dependency projects
• exception handling on EnsureTypeIsLoaded
• various fixes in file handling layer
• improved handling of variables assigned to variables in the Monitor
• handling of multiple CPUs with different configurations in GDB
• STM32F413 RCC address
• DDR mapping in PolarFire SoC
• TCM memory size in miv_rv32

Improvements in peripherals:

• NVIC
• STM32F4_RCC
• STM32_ADC
• STM32_GPIOPort
• MiV_CoreGPIO
• GigaDevice_GD25LQ
• MC3635
• SynopsysEthernetMAC
• LiteSDCard_CSR32
• ResetPin
• HPSHostController

For installation instructions, see the README.

Added platforms:

• Xtensa sample controller stub
• MIMXRT1064-EVK
• STM32L552
• ARVSOM
• BeagleV StarLight
• Sparc GR716
• RISC-V virt
• S32K118 with LPIT, LPTMR, GPIO, Clock generator mock
• STM32G0
• STM32F412
• STM32H743
• MIV_RV32

Added models:

• new models for i.MX RT 1064: PWM, timer, ADC, LPSPI, Flex SPI, TRNG
• new models for nRF52840: RNG, Radio, Watchdog, ECB, PPI infrastructure
• new models for STM32: ADC, slave CAN, PWR, watchdog
• new models for OpenTitan: flash controller, timer, PLIC, HMAC, AES, KMAC, ROM controller, Key manager, Reset manager
• new models for Polarfire SoC: system services, user crypto features (RNG and RSA), Mustein GPU and various fixes to platform description
• new model for Zynq 7000: XADC
• new generic models:
  • generic SPISensor
  • HostCamera device
  • TrivialUart
  • HPSHostController - fake I2C host master device for communicating with simulated devices
  • GigaDevice_GD25LQ - initial model
  • VirtIO block device model

Added demos:

• Murax SoC with verilated UART with simple echo demo
• LiteX with verilated CFU running CFU Playground demo
• Zynq with verilated FastVDMA running Linux
• NRF52840 BLE demo running Zephyr central_hr and peripheral_hr samples
• Leon3 running Zephyr shell
• GR716 running Zephyr shell
• Xtensa sample controller running Zephyr “Hello World" sample

Added core features:

• RISC-V: vector extension 1.0 support
• Xtensa architecture support
• RISC-V: access to proper set of registers + custom registers from GDB
• RISC-V: support for Custom Function Unit extensions
• WFE support on ARM cores
• uninterruptible debugging option to all architectures
• floating point support to Cortex-M platforms
• basic support for ARM 64-bit registers
• Cortex-M33 stub
• Sparc: added CSR register and exposed FSR register

Added features:

• primary selection copy support in TermSharp
• support for asciinema UART dumps
• support for native library communication in verilated peripherals
• APB3 bus implementation for VerilatorIntegrationLibrary
• support for loading HEX files
• video capture mechanism with host camera integration
• startup parameter for specifying the config file
• register access keywords for Robot Framework integration
• support VideoAnalyzer on Windows
• option to stop on first error when running tests
• option to save failed test logs
• opcodes counting mechanism, along with RISC-V opcodes files parser
• execution tracing mechanism
• Wireshark support on Windows
• seL4-aware GDB debug support
• BLE wireless medium including Wireshark support
• gdb_compare script allowing to compare execution of two GDB instances, for example one connected to Renode and one to hardware
• support for vector registers in GDB
• CPU Id parameter in ARM cores
• option to control timestamp format and visibility in LoggingUartAnalyzer
• option to skip library fetch during build
• option to flush terminal history when connecting via socket
• support for external, bus-connected MMU

Changed:

• bumped Robot Framework version to 4.0.1
• RobotFramework: log entries keywords now accept regex patterns
• STM: renamed some UART ports to USART
• ZynqEthernet: removed and replaced with CadenceGEM
• Zedboard: updated demo to Linux 5.10
• reworked CPU halting
• added CRC to packets sent by NetworkServer
• RISC-V: added logs on unhandled CSR accesses
• improved build time by changes to TermSharp project organization
• various updates to STM32F746 CPU definition
• added limit to displayed command history in AntShell
• moved output of Robot tests to current directory when running on Windows
• XWT events are now queued in GTK engine
• added option to reconnect to SocketServerProvider
• explicitly used XZ compression with pacman
• added option to limit function names logging to unique entries, vastly improving performance
• removed dependency to realpath from build and run scripts
• removed dependency to ZeroMQ
• renamed EOSS3_SPIMaster to DesignWare_SPI
• dropped Fedora version indicator from packages
• optimized RISC-V PMP handling
• reworked PlatformLevelInterruptController to operate on contexts instead of targets
• added O/H/W write commands to ArduinoLoader
• enabled TLS 1.1 and TLS 1.2 in CachingFileFetcher
• improved multicore debugging support in GDB
• allowed to reuse testers in Robot tests
• added option to safely include the same C# file multiple times during one Renode run
• added tests.yaml, containing all Robot tests, to all packages
• add debug mode for all architectures disabling interrupts when stepping over guest code
• simplified fixture selection when running tests
• allowed unaligned memory access by default in IbexRiscV32
• added GBD support for VS bits in MSTATUS register
• added interrupts support in verilated peripherals
• added support for CPU registers wider than 64-bits in Renode (C# part, not tlibs)
• improved and unified the --plain mode handling
• refactored the disassembly handling subsystem
• improved GDB packets handling performance
• added option to control serialization mode in the configuration file
• added optional compiled files cache
• improved handling of exceptions at the C/C# boundary
• flattened the TimeFramework structure to increase performance
• improved performance of handling of truncated translation blocks
• improved performance of TermSharp height map calculations and row handling
• added several tlib performance optimizations
• added the synchronized timers emulation mode
• added support for the flow control in UART
• added support for bright colors to TermSharp
• added basic VSCode launch configurations for Renode on Mono
• unified renode and renode-test scripts names across all packages
• added support for per-core peripheral registration
• added option to the build script to export the build directory
• improved performance of ELF reloading
• updated Conda build scripts to better work with the latest Renode, improved Windows support
• added option to configure step for clock entries
• improved startup performance by skipping analysis of uninteresting assemblies in TypeManager
• tied the AutoRepaintingVideo refresh frequency to the virtual time flow
• enabled passing the -e parameter to Renode even when providing a script file parameter
• added option to preserve temporary files from Robot tests
• added a source of a log message to the log tester
• Provides and Requires keywords now use state snapshots

Fixed:

• CPU endianness handling in GDB register accesses
• SPARC WRASR and CASA instructions
• SPARC registers handling in GDB
• memory invalidation on writes in MappedMemory
• ARM instructions: ASX, SAX, SUB16 and UQSUB
• symbol name mangling on MacOS
• updating PC before raising MMU exception on RISC-V
• unaligned ld_phys handling, resolves problems of possible memory corruption
• possible race conditions in TerminalTester
• IO access path selection in tlib
• support for big-endian peripherals
• running tests in sequential mode
• HiFive Unleashed platform description including PHY advertisement and RAM size
• Ethernet PHY advertisement on the Zedboard platform
• cross-endian bus accesses
• endian conversion wrappers for untranslated accesses
• registers mapping of fflags/frm/fcsr, resolving GDB registers XML generation
• running tests when the build phase failed
• it-status unit test
• added LibLLVM to all packages
• whitespace handling in resc scripts on Windows
• occasional assertion fail when loading ELF files
• setting breakpoints on virtual addresses
• MicroPython tests
• installation on Linux with a separate /opt mount point
• demangling symbols from the anonymous namespace
• SoftFloat's type conversion functions
• illegal instruction exception on wrong CSR access on RISC-V
• support for quad words access on the system bus
• possible memory leak in tlib
• improved precision of calculations in BasicClockSource and ComparingTimer Fixed
• support for various versions of standard libraries on Linux hosts (libdl, libutil, etc)
• libc dependencies for the Renode portable package
• invalidation of translation blocks on writes
• handling big offsets in MappedMemory
• ARM-M PRIMASK and xPSR handling
• PowerPC registers listing in GDB
• improved tlib debugging by not omitting the frame pointer on debug build
• fixed sfence.vma instruction implementation for RISC-V
• potential math errors (underflows/overflows) when handling the virtual time
• handling input redirected from file in the console mode
• prevented GdbStub from sending telnet config bytes on new connections
• serialization of paused state
• ad-hoc compiler support in the portable package
• flushing of log tester
• UartPtyTerminal serialization
• reporting the exit code in renode-test
• RISC-V custom CSRs handling
• resetting of a machine from the context of another machine
• thread-safety of interrupt handling mechanism
• occasional dependency fail on static constructors

Improvements in peripherals:

• CoreLevelInterruptor
• PlatformLevelInterruptController
• NVIC
• CortexAPrivateTimer
• BMA180
• CC1200
• Micron_MT25Q
• SynopsysEthernetMAC
• K6xF_Ethernet
• CadenceGEM
• OV2640
• GaislerMIC
• PL011
• EFR32_USART
• LowPower_UART
• OpenTitan_UART
• OpenTitan_GPIO
• IMXRT_ADC
• IMXRT_LPSPI
• LPUART
• STM32F7_I2C
• STM32_UART
• STM32 RTC
• STM32_TIMER
• STM32DMA
• STMCAN
• EXTI
• NRF52840_CLOCK
• NRF52840_Timer
• NRF52840 GPIO
• LiteX_I2S
• Litex_GPIO
• MPFS_PDMA
• MPFS_DDRMock
• Gaisler_GPTimer