[Intel GPU] int4 WOQ gemm XPU Support #137566

ZhiweiYan-96 · 2024-10-09T07:24:35Z

Stack from ghstack (oldest at bottom):

cc @jgong5 @mingfeima @XiaobingSuper @sanchitintel @ashokei @jingxu10 @gujinghui @EikanWang @fengyuan14 @guangyey

[ghstack-poisoned]

pytorch-bot · 2024-10-09T07:24:39Z

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NEW FAILURES - The following jobs have failed:

xpu / linux-jammy-xpu-2025.0-py3.9 / test (default, 1, 4, linux.idc.xpu) (gh)
inductor/test_torchinductor_codegen_dynamic_shapes.py::DynamicShapesCodegenGPUTests::test_pow_by_natural_log2_dynamic_shapes_dynamic_shapes_xpu
xpu / linux-jammy-xpu-2025.0-py3.9 / test (default, 2, 4, linux.idc.xpu) (gh)
export/test_cpp_serdes.py::CppSerdesTestExport::test_device_to_gpu_cpp_serdes
xpu / linux-jammy-xpu-2025.0-py3.9 / test (default, 3, 4, linux.idc.xpu) (gh)
export/test_retraceability.py::RetraceExportTestExport::test_device_to_gpu_retraceability_strict
xpu / linux-jammy-xpu-2025.0-py3.9 / test (default, 4, 4, linux.idc.xpu) (gh)
inductor/test_torchinductor.py::GPUTests::test_pow_by_natural_log2_dynamic_shapes_xpu

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ghstack-source-id: 403047a Pull Request resolved: #137566

ZhiweiYan-96 · 2024-10-09T07:27:48Z

@zhuyuhua-v Could you please review the PR?

EikanWang · 2024-10-10T01:27:13Z

aten/src/ATen/native/mkldnn/xpu/detail/WoQMatmul.cpp

+      "oneDNN input matrixes must have the same ranks");
+  TORCH_CHECK(result.defined(), "oneDNN matmul result should be defined");
+
+  at::Device curDevice = at::Device(at::kXPU, at::xpu::current_device());


Please unify the code style. curDevice -> cur_device.

Thanks for you suggestions, the naming has been changed.

EikanWang · 2024-10-10T01:31:30Z

aten/src/ATen/native/mkldnn/xpu/detail/WoQMatmul.cpp

+    mb = dst.size(0);
+    TORCH_CHECK(
+        mb == m1.size(0) && mb == m2.size(0),
+        "batch size mismatch, dst mb: ",


Is mb a common term? Can users fully understand the exact meaning of mb?

Thanks for your suggestions, mb means minibach here, but i review the code and remove mb in the code since int4_gemm has no need to handle batch currently.

EikanWang · 2024-10-10T01:35:38Z

aten/src/ATen/native/mkldnn/xpu/detail/WoQMatmul.cpp

+  scale_usr_md = dnnl::memory::desc(scale_dims, scale_user_dt, scale_strides);
+  zp_usr_md = dnnl::memory::desc(zp_usr_dims, zp_user_dt, zp_usr_strides);
+  dst_usr_md = dnnl::memory::desc(dst_dims, dst_usr_dt, dst_strides);
+  // STEP4: create dnnl::memory


Where are STEP 2 and STEP 3?

I have removed these kind of comments and add new comments in the codes.

EikanWang · 2024-10-10T01:46:28Z

aten/src/ATen/native/mkldnn/xpu/detail/WoQMatmul.cpp

+  args.insert({DNNL_ARG_ATTR_ZERO_POINTS | DNNL_ARG_WEIGHTS, zp_usr_m});
+
+  sycl::event matmul_event = dnnl::sycl_interop::execute(matmul_p, stream, args, deps);
+  if (!dst.is_same(result))


When is dst not the same as result?

These issues roots from the woq matmul is ported from regular matmul. int4_gemm has no need to consider dst is not same as result currently, I have removed the code.

EikanWang · 2024-10-10T01:47:09Z

aten/src/ATen/native/mkldnn/xpu/detail/WoQMatmul.cpp

+  sycl::event matmul_event = dnnl::sycl_interop::execute(matmul_p, stream, args, deps);
+  if (!dst.is_same(result))
+    result.copy_(dst);
+  result = resize_as_onednn_mat1(mat1_, result);


When is resize_as_onednn_mat1 required?

EikanWang · 2024-10-10T01:56:39Z

aten/src/ATen/native/mkldnn/xpu/detail/WoQMatmul.cpp

+  args.insert({DNNL_ARG_SCRATCHPAD, scratchpad_memory});
+
+  if (attr.with_binary())
+    attr.construct_post_binary(matmul_pd, args);


attr constructs the post binary. However, dnnl::post_ops po = attr.extract_post_ops(dst); has extracted the post ops and pattr.set_post_ops(po); has assigned the post op to matmul primitive attribute. Is it a valid behavior?

int4 would have no post-ops currently, i have removed the code, thanks.

EikanWang · 2024-10-10T01:58:07Z

aten/src/ATen/native/mkldnn/xpu/detail/WoQMatmul.cpp

+      dnnl::memory::data_type::s8);
+  // Set fpmath mode with `apply_to_int=true` to apply fpmath mode behavior to
+  // integral primitives (in this example, matmul).
+  pattr.set_fpmath_mode(dnnl::fpmath_mode::f16, true);


OneDNN supports both f16 and bf16. Why do we need to constrain the dtype?

We know have a control statement to determine which dtype is used for fpmath_mode, thanks. However, bf16 would have runtime issue in oneDNN at current version. The bf16 dtype is valid in newer version of onednn.

ZhiweiYan-96 · 2024-10-15T06:47:16Z

@liangan1 Could you please review the PR?

liangan1 · 2024-10-15T23:14:00Z

aten/src/ATen/native/mkldnn/xpu/detail/WoQMatmul.cpp

+  TORCH_CHECK(
+      dims == mat1.dim() && dims == mat2.dim(),
+      "oneDNN input matrixes must have the same ranks");
+  TORCH_CHECK(result.defined(), "oneDNN matmul result should be defined");


Since you have flatten the mat1 and mat2 into dims=2 and the result is also 2 dimension empty tensor. when will dim=3 and result is not defined? Can you show a example?

Some logic is too old, and we have removed such weird code in gemm integration now.

liangan1 · 2024-10-15T23:21:06Z

aten/src/ATen/native/mkldnn/xpu/detail/WoQMatmul.cpp

+    Attr attr,
+    const c10::optional<Tensor>& g_idx,
+    const std::vector<sycl::event>& deps,
+    Tensor b_raw = at::Tensor()) {


Change to bias_raw?

bias is not presented in weight_int4pack_mm API, and I have removed bias related code in newest commit. Thanks for your suggestions.

liangan1 · 2024-10-15T23:31:37Z

aten/src/ATen/native/mkldnn/xpu/detail/WoQMatmul.cpp

+              (b.size(0) == 1 && b.size(1) == 1),
+          "matmul supports [m, n] or [1, n] or [m, 1] or [1, 1] when bias dim is 2 ...");
+      if (b.size(0) == 1 && b.size(1) == 1)
+        b = b.expand({1, n}).contiguous();


In other case(e.g., b.dim()=1/3/0), you always expand the b to the same dim to m1. Whether it works when the m1.dim()==3 while b.dim()==2? According to the doc of onednn: "all tensors (including bias
, if it exists) must have the same number of dimensions."

These codes have been removed by me as it is bias -related. Thanks for you reminding.

liangan1 · 2024-10-15T23:40:11Z

aten/src/ATen/native/mkldnn/xpu/detail/WoQMatmul.cpp

+  auto m2_usr_dt = get_onednn_dtype(m2);
+  auto scale_user_dt = get_onednn_dtype(scale_); // half <==> fp16
+  //   auto zp_user_dt = dnnl::memory::data_type::s4; // int32, representing 8xint4
+  auto zp_user_dt = get_onednn_dtype(zp_);


Suggest to change xxx_user_xxx to xxx_usr_xxx to unify the style. Due to onednn support different data types , suggest to change to "e.g., half<==>f16"

liangan1 · 2024-10-16T00:31:42Z

aten/src/ATen/native/mkldnn/xpu/detail/WoQMatmul.cpp

+  return output.view_symint(sizes);
+}
+
+sycl::event woq_matmul_int4(


Suggest to add more function description here. e.g. the activation data type supported, data layout information for both inputs. etc...

More detailed description is added in older commits.

liangan1 · 2024-10-16T02:26:28Z

aten/src/ATen/native/mkldnn/xpu/detail/WoQMatmul.cpp

+
+  m2_usr_dims = {compressed_k, n};
+  scale_dims = {num_groups, n};
+  zp_dims = {1};


The dims of zp_dims is not aligned with the original zp inputs. With this limitation, only the symmetric or per-tensor quantization is supported. Pls add the comments about this limitation of oneDNN.

OneDNN provides us with a way to support asymmetry, allowing us to handle asymmetrical scenarios. I'm currently testing it, and if it works, I will modify it here to support both symmetric and asymmetric logic.

airMeng

There should be a prepack process since OneDNN doesn't support the most popular layout

[ghstack-poisoned]

ghstack-source-id: 451a44c Pull Request resolved: #137566

[ghstack-poisoned]

ghstack-source-id: ab34a0e Pull Request resolved: #137566

liangan1 · 2024-11-05T05:00:27Z

There should be a prepack process since OneDNN doesn't support the most popular layout

https://github.com/intel/torch-xpu-ops/pull/1035/files This PR is used to do int4 weight prepack.

[ghstack-poisoned]

ghstack-source-id: 9863ceb Pull Request resolved: #137566

[ghstack-poisoned]

ghstack-source-id: 6eb581c Pull Request resolved: #137566

[ghstack-poisoned]

ghstack-source-id: 6919d03 Pull Request resolved: #137566

liangan1 · 2024-11-28T08:02:06Z

test/xpu/test_gemm.py

+                b, n_bit=4, q_group_size=q_group
+            )
+            # b_int4pack [n, k//8]
+            b_int4pack = torch._convert_weight_to_int4pack(


This should be b_int4pack [k//8, n]

Thanks for reminding, I have modified the description here.

liangan1 · 2024-11-29T02:00:32Z

aten/src/ATen/native/mkldnn/xpu/detail/WoQMatmul.cpp

+  sizes[sizes.size() - 1] = n;
+  return output.view_symint(sizes);
+}
+


Should remove this?

Yes, these codes have been removed in newest commit, thanks for reminding.

liangan1 · 2024-11-29T02:02:26Z

aten/src/ATen/native/mkldnn/xpu/detail/WoQMatmul.cpp

+  Tensor m1 = is_onednn_matmul_strides(mat1_) ? mat1_ : mat1_.contiguous();
+  //m2_ may be a 4 dims fake tensor in torchAO with shape {N / 8, K / (16 * innerKTiles), 32, innerKTiles / 2}
+  //Tensor m2 = mat2_.flatten(0, -2); //ToDo: change to the fke shape: mat2_.flatten(0, -2); // N1
+  Tensor m2 = is_onednn_matmul_strides(mat2_) ? mat2_ : mat2_.contiguous();


Remove this comments.

liangan1 · 2024-11-29T02:08:55Z

aten/src/ATen/native/mkldnn/xpu/detail/Matmul.cpp

-  auto expected_m1_md = matmul_pd.src_desc();
-  auto expected_m2_md = matmul_pd.weights_desc();
-  auto expected_dst_md = matmul_pd.dst_desc();
-


Need to remove this part.

liangan1 · 2024-11-29T02:10:46Z

torch/testing/_internal/common_quantization.py

-    zeros = min_val + scales * (2 ** (n_bit - 1))
+    zeros = min_int - min_val.div(scales).round()
+    zeros = torch.clamp(zeros, min_int, max_int)
+    zeros = zeros.to(torch.int8)
    assert torch.isnan(zeros).sum() == 0


This is also used in tinygemm, should not change this one.

Thanks for pointing out, I have moved the codes to xpu/test_gemm.py

EikanWang · 2025-03-03T07:41:41Z

aten/src/ATen/native/mkldnn/xpu/detail/oneDNN.h

+    const at::Tensor& zp, // [k/group_size, N]
+    int64_t group_size,
+    Attr attr,
+    const std::vector<sycl::event>& deps = {});


why does this operation require deps?

Formerly, fs1 requires we add events at oneDNN integration layer for profiling purposes. For me, it is just intended to have consistent API with conv/gemm. Do we need to remove this?

EikanWang · 2025-03-03T07:45:14Z

aten/src/ATen/native/mkldnn/xpu/detail/oneDNN.h

+    const at::Tensor& scale, // [K/group_size, N]
+    const at::Tensor& zp, // [k/group_size, N]
+    int64_t group_size,
+    Attr attr,


Suggested change

Attr attr,

std::optional<Attr> attr = std::nullopt,

will removed attr, as we do not append post-op currently.

EikanWang · 2025-03-03T07:46:38Z

aten/src/ATen/native/mkldnn/xpu/detail/oneDNN.h

+    const at::Tensor& zp, // [k/group_size, N]
+    int64_t group_size,
+    Attr attr,
+    const std::vector<sycl::event>& deps = {});


Suggested change

const std::vector<sycl::event>& deps = {});

const std::optional<std::vector<sycl::event>>& deps = std::nullopt);

EikanWang · 2025-03-03T07:48:23Z

aten/src/ATen/native/mkldnn/xpu/Blas.cpp

+
+  // qscale:[K/qGroupSize, N]
+  // qzp:[K/qGroupSize, N]
+  woq_matmul_int4(C, A, B, qScale, qZeros, qGroupSize, onednn::Attr());


Is there any case that we need to fuse other operations? What's the motivation here to provide attributes?

EikanWang · 2025-03-03T07:52:49Z

aten/src/ATen/native/mkldnn/xpu/Blas.cpp

+    const Tensor& A,
+    const Tensor& B,
+    int64_t qGroupSize,
+    const Tensor& qScale,
+    const Tensor& qZeros) {


@ZhiweiYan-96 , the code style of Blass.cpp is snake_case, why is the style of these variables camelCase?

hi, @EikanWang The naming style here is for aligning with other backend like cuda (https://github.com/pytorch/pytorch/blob/main/aten/src/ATen/native/cuda/int4mm.cu#L1097) and cpu (https://github.com/pytorch/pytorch/blob/main/aten/src/ATen/native/LinearAlgebra.cpp#L3461)

EikanWang · 2025-03-03T07:55:48Z

aten/src/ATen/native/mkldnn/xpu/detail/WoQMatmul.cpp

+
+  at::Device cur_device = at::Device(at::kXPU, at::xpu::current_device());
+  auto engine = GpuEngineManager::Instance().get_engine(cur_device);
+  auto stream = GpuStreamManager::Instance().get_stream();


@ZhiweiYan-96 , may I know where the guard code to ensure all the input tensors to be on the same device?

EikanWang · 2025-03-03T08:05:18Z

aten/src/ATen/native/mkldnn/xpu/detail/WoQMatmul.cpp

+  dst_md = dnnl::memory::desc(dst_dims, dst_dt, dst_strides);
+
+  std::unordered_map<int, dnnl::memory> args;
+  dnnl::post_ops po = attr.extract_post_ops(dst);


The po should be useless. Has this file been added to torch linter?

Post-ops is not required at present. We can remove the post op and added it back when it is necessary.

All file in xpu/detail/*.cpp is in linter checking list. I met this before. It should caused that, linter does not check this noused style issue.

[ghstack-poisoned]

guangyey · 2025-03-25T02:07:53Z

aten/src/ATen/native/mkldnn/xpu/detail/WoQMatmul.cpp

+  auto engine = GpuEngineManager::Instance().get_engine(cur_device);
+  auto stream = GpuStreamManager::Instance().get_stream();


Suggested change

auto engine = GpuEngineManager::Instance().get_engine(cur_device);

auto stream = GpuStreamManager::Instance().get_stream();

auto& engine = GpuEngineManager::Instance().get_engine();

auto& stream = GpuStreamManager::Instance().get_stream();

thanks for the information. Has updated the code.

[ghstack-poisoned]

ZhiweiYan-96 · 2025-03-25T08:33:17Z

Update

Remove all usage of post-ops code (attr, post-op). The reason is that no post-op requirement for int4 gemm currently.
Remove sycl::event related code. We will add this back when it is really required.

[ghstack-poisoned]

pytorchmergebot · 2025-04-08T01:54:01Z

Rebased gh/ZhiweiYan-96/47/orig onto refs/remotes/origin/viable/strict because #147962 was rebased, please pull locally before adding more changes (for example, via ghstack checkout https://github.com/pytorch/pytorch/pull/137566)

[ghstack-poisoned]

pytorchmergebot · 2025-04-08T15:13:20Z

Starting merge as part of PR stack under #147962

pytorchmergebot · 2025-04-08T15:30:03Z

Starting merge as part of PR stack under #147962

…tration (#147962) Pull Request resolved: #147962 Approved by: https://github.com/jerryzh168, https://github.com/guangyey, https://github.com/EikanWang ghstack dependencies: #137566 Co-authored-by: xiaolil1 <xiaoli.liu@intel.com>

Pull Request resolved: pytorch#137566 Approved by: https://github.com/liangan1, https://github.com/guangyey, https://github.com/EikanWang Co-authored-by: xiaolil1 <xiaoli.liu@intel.com>

…tration (pytorch#147962) Pull Request resolved: pytorch#147962 Approved by: https://github.com/jerryzh168, https://github.com/guangyey, https://github.com/EikanWang ghstack dependencies: pytorch#137566 Co-authored-by: xiaolil1 <xiaoli.liu@intel.com>

Pull Request resolved: pytorch#137566 Approved by: https://github.com/liangan1, https://github.com/guangyey, https://github.com/EikanWang Co-authored-by: xiaolil1 <xiaoli.liu@intel.com>

…tration (pytorch#147962) Pull Request resolved: pytorch#147962 Approved by: https://github.com/jerryzh168, https://github.com/guangyey, https://github.com/EikanWang ghstack dependencies: pytorch#137566 Co-authored-by: xiaolil1 <xiaoli.liu@intel.com>

ghstack-source-id: c2c4f90 Pull Request resolved: pytorch/pytorch#137566

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[Intel GPU] int4 WOQ gemm XPU Support

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[RFC][API-Unstable]A16W4 on XPU Device #153019

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	const std::vector<sycl::event>& deps = {});
	const std::optional<std::vector<sycl::event>>& deps = std::nullopt);

		auto engine = GpuEngineManager::Instance().get_engine(cur_device);
		auto stream = GpuStreamManager::Instance().get_stream();

[Intel GPU] int4 WOQ gemm XPU Support #137566

[Intel GPU] int4 WOQ gemm XPU Support #137566

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liangan1 commented Nov 5, 2024

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ZhiweiYan-96 commented Oct 9, 2024 •

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pytorch-bot bot commented Oct 9, 2024 •

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ZhiweiYan-96 Dec 16, 2024 •

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liangan1 Oct 15, 2024 •

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