This is a re-release of the 2024011101-tock-ci-0 tag, with an issue in the requirements.txt file fixed.

This is not a proper release. The revision behind this tag carries patches required for the execution of Tock's litex-sim-ci workflow which are not yet available in the upstream package set. This tag ensures that this revision will be retained in the repository, and allows publishing pre-built artifacts via a GitHub pre-release.

The attached build artifacts may reproduce, in part or as a whole, some of the build inputs used to build these artifacts. Such reproductions retain the terms and conditions under which they were licensed within the original build input component. The license of this repository only applies to files maintained in this repository and unless specified otherwise. Specifically, the sources of some of the attached build artifacts are:

• litex_patched.zip: https://github.com/enjoy-digital/litex
• pythondata-cpu-vexriscv_patched.zip: https://github.com/litex-hub/pythondata-cpu-vexriscv

This release contains the generated build artifacts for the tock-litex commit 4d97b75d31.

The included boards are:

• digilent_arty_a7-35t.zip: Tock board definition
• digilent_arty_a7-100t.zip: Tock board definition
• digilent_nexys_video.zip

The various LiteX package versions are listed in the nix-litex[1] repository at revision 75fb0a2b9b under pkgs/litex_packages.toml or in the requirements.txt file of this repository respectively. A couple packages are patched (pythondata-cpu-vexriscv, litex, litex-boards). The former two patched packages are included in the GitHub release artifacts associated with this tag, and pulled in bythe requirements.txt file.

The Xilinx FPGA bitstreams are built using Xilinx Vivado 2022.2.

The attached build artifacts may reproduce, in part or as a whole, some of the build inputs used to build these artifacts. Such reproductions retain the terms and conditions under which they were licensed within the original build input component. The license of this repository only applies to files maintained in this repository and unless specified otherwise. Specifically, the sources of some of the attached build artifacts are:

• litex_patched.zip: https://github.com/enjoy-digital/litex
• pythondata-cpu-vexriscv_patched.zip: https://github.com/litex-hub/pythondata-cpu-vexriscv

[1]: https://sr.ht/~lschuermann/nix-litex/, additional mirrors in litex-pkgs.nix

This is not a proper release. The revision behind this tag carries patches required for the execution of Tock's litex-sim-ci workflow which are not yet available in the upstream package set. This tag ensures that this revision will be retained in the repository, and allows publishing pre-built artifacts via a GitHub pre-release.

The attached build artifacts may reproduce, in part or as a whole, some of the build inputs used to build these artifacts. Such reproductions retain the terms and conditions under which they were licensed within the original build input component. The license of this repository only applies to files maintained in this repository and unless specified otherwise. Specifically, the sources of some of the attached build artifacts are:

• litex_patched.zip: https://github.com/enjoy-digital/litex
• pythondata-cpu-vexriscv_patched.zip: https://github.com/litex-hub/pythondata-cpu-vexriscv

This is not a proper release. The revision behind this tag carries patches required for the execution of Tock's litex-sim-ci workflow which are not yet available in the upstream package set. This tag ensures that this revision will be retained in the repository, and allows publishing pre-built artifacts via a GitHub pre-release.

The attached build artifacts may reproduce, in part or as a whole, some of the build inputs used to build these artifacts. Such reproductions retain the terms and conditions under which they were licensed within the original build input component. The license of this repository only applies to files maintained in this repository and unless specified otherwise. Specifically, the sources of some of the attached build artifacts are:

• litex_patched.zip: https://github.com/enjoy-digital/litex
• pythondata-cpu-vexriscv_patched.zip: https://github.com/litex-hub/pythondata-cpu-vexriscv

This is not a proper release. The revision behind this tag carries patches required for the execution of Tock's litex-sim-ci workflow which are not yet available in the upstream package set. This tag ensures that this revision will be retained in the repository, and allows publishing pre-built artifacts via a GitHub pre-release.

The attached build artifacts may reproduce, in part or as a whole, some of the build inputs used to build these artifacts. Such reproductions retain the terms and conditions under which they were licensed within the original build input component. The license of this repository only applies to files maintained in this repository and unless specified otherwise. Specifically, the sources of some of the attached build artifacts are:

• litex_patched.zip: https://github.com/enjoy-digital/litex
• pythondata-cpu-vexriscv_patched.zip: https://github.com/litex-hub/pythondata-cpu-vexriscv

This release contains the generated build artifacts for the tock-litex commit 822a942a5c.

The included boards are:

• digilent_arty_a7-35t.zip: Tock board definition
• digilent_arty_a7-100t.zip: Tock board definition
• digilent_nexys_video.zip

The various LiteX package versions are listed in the nix-litex1 repository at revision b9498679d4 under pkgs/litex_packages.toml or in the requirements.txt file of this repository respectively.

The Xilinx FPGA bitstreams are built using Xilinx Vivado 2020.1.

The attached build artifacts may reproduce, in part or as a whole, some of the build inputs used to build these artifacts. Such reproductions retain the terms and conditions under which they were licensed within the original build input component. The license of this repository only applies to files maintained in this repository and unless specified otherwise. Specifically, the sources of some of the attached build artifacts are:

• litex_patched.zip: https://github.com/enjoy-digital/litex
• pythondata-cpu-vexriscv_patched.zip: https://github.com/litex-hub/pythondata-cpu-vexriscv

This release contains the generated build artifacts for the tock-litex commit ab36660c22.

The included boards are:

• digilent_arty_a7-35t.zip: Tock board definition
• digilent_arty_a7-100t.zip: Tock board definition
• digilent_nexys_video.zip

The various LiteX package versions are listed in litex-pkgs.toml or requirements.txt respectively.

The Xilinx FPGA bitstreams are built using Xilinx Vivado 2020.1.

This release contains the generated build artifacts for the tock-litex commit 18c0282c9c.

This release is a follow-up to tag 2021072001, which had a regression in the VexRiscv CPU's PMP implementation, not supporting the TOR addressing mode any longer. This is required for the current PMP implementation in Tock. Thus, this commit reverts the VexRiscv CPU version.

The included boards are:

• digilent_arty_a7-35t.zip: Tock board definition
• digilent_nexys_video.zip

The source packages' versions are:

• litedram: 4326fe7f36699a
• liteeth: 947ed037202a99
• liteiclink: 3d8ecdbcf9f026
• litepcie: 68334fd93d078c
• litescope: 72c9930705ccc5
• litespi: 51eabb52248ab5
• litex-boards: 4b48f15265c902
• litex: e0d5a7bff55923
• migen: 0.9.2
• pythondata-cpu-vexriscv: 7f9db486d40206 (with patches of lschuermann/litex-vexriscv-custom)
• pythondata-misc-tapcfg: 0e6809132b7a42
• pythondata-software-compiler-rt: 2020.08

The Xilinx FPGA bitstreams are built using Xilinx Vivado 2020.1.

This release contains the generated build artifacts for the tock-litex commit 7fcbefac7f.

This release includes a version of the VexRiscv CPU in which the PMP implementation does not support the TOR addressing mode and is thus incompatible with the current implementation of Tock.

The included boards are:

• digilent_arty_a7-35t.zip: Tock board definition
• digilent_nexys_video.zip

The source packages' versions are:

• litedram: 4326fe7f36699a
• liteeth: 947ed037202a99
• liteiclink: 3d8ecdbcf9f026
• litepcie: 68334fd93d078c
• litescope: 72c9930705ccc5
• litespi: 51eabb52248ab5
• litex-boards: 4b48f15265c902
• litex: e0d5a7bff55923
• migen: 0.9.2
• pythondata-cpu-vexriscv: a17f86c94c11da (with patches of lschuermann/litex-vexriscv-custom)
• pythondata-misc-tapcfg: 0e6809132b7a42
• pythondata-software-compiler-rt: 2020.08

The Xilinx FPGA bitstreams are built using Xilinx Vivado 2020.1.

Changelog:

• Update LiteX and associated packages, add litepcie, litehyperbus, litespi.

• Do not reference the Nix store in the required input files for Xilinx Vivado bitstream builds (vendor Verilog inputs).

• Update the pinned nixpkgs revision for release builds to a 21.05 snapshot.

• Avoid referencing the Vivado installer source in the resulting Nix derivation, such that it can be garbage collected properly.

This release contains the generated build artifacts for the tock-litex commit 46fab5338d.

The included boards are:

• arty_a7-35t.zip: Tock board
  definition
• nexys_video.zip

The source package's versions are:

• litedram: f17037fdb22c87
• liteeth: 6c3af746e28f55
• liteiclink: 0980a7cf4ffcb0
• litescope: f7a9672284b01f
• litex: 11f7416e3603bf
• litex-boards: ef662035b13a65
• migen: 0.9.2
• pythondata-cpu-vexriscv: 7f9db486d40206 (with custom patches)
• pythondata-misc-tapcfg: 0e6809132b7a42
• pythondata-software-compiler-rt: 2020.08

The Xilinx FPGA bitstreams are built using Xilinx Vivado 2020.1.

Changelog:

• Do not require a Scala installation anymore. Prebuilt archives of the customized VexRiscv CPUs are now downloaded from https://github.com/lschuermann/litex-vexriscv-custom/releases

• Add builds for the Digilent Nexys Video FPGA board.

• Update the LiteX packages.

• Improve documentation.