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Xiretza
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@Xiretza Xiretza commented Feb 28, 2022

This implements LCS-2016-002, at least in the analyzer. This is required in order for the VHDL-2019 standard libraries to analyze.

@Xiretza Xiretza mentioned this pull request Feb 28, 2022
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@tgingold
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tgingold commented Mar 1, 2022

Style issue: please, add a space before opening parenthesis.

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Xiretza commented Mar 1, 2022

Ah, I forgot about that, fixed.

@umarcor umarcor added the FeaReq: VHDL-2019 Requested feature addition related to VHDL-2019. label Mar 1, 2022
@umarcor umarcor added this to the v3.0 milestone Mar 1, 2022
@tgingold tgingold merged commit 182770c into ghdl:master Mar 1, 2022
@Xiretza Xiretza deleted the lcs-2016-002 branch March 12, 2022 21:25
@JimLewis
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Does this work now in GHDL? Very interested in this one.

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tgingold commented Feb 19, 2023 via email

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JimLewis commented Feb 7, 2024

Has anyone tested this feature. I have plans to create a package that uses it.

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4 participants