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Support to evaluate PSL endpoints in VHDL code #45

@tmeissner

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@tmeissner

GHDL already supports the PSL endpoint statement, which triggers at the last cycle of a sequence which was hit. However, you only can evaluate the endpoint in PSL code. In other simulators it is possible to read the value of the endpoint in VHDL code like this:

-- psl endpoint e_test is {req; not(grant); grant}@rising_edge(clk);

process is
begin
  wait until e_test;
  report "e_test hit";
  wait;
end process;

You can find an other example here: http://www.cvcblr.com/blog/?p=810

I don't know, if evaluating PSL endpoints in VHDL is defined in the PSL standard, but the tools that I now (Modelsim/Questa) support that. I will try on edaplayground, if Riviera also supports that, but I think it does. In the IEEE PSL standard endpoint was replaced by the ended() function, which is similar. But GHDL don't supports any PSL functions, so it would be a more easy way to enhance the already supported endpoint statement.

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