Hi,

I have a VHDL procedure that assigns a value to an output, then later attempts to read the output :

procedure myproc (signal clk : in std_logic; signal a : out std_logic) is 
begin
    a <= '1';
    wait until rising_edge(clk);
    if a='1' then  -- etc 
)

When I try to compile I get error : signal interface "a" cannot be read

Is this a bug? I thought reading outputs was legal in VHDL-2008 ?

Is there any way to downgrade the error to a warning (I tried -frelaxed but without success)

(I realise the above is bad practice, but its not my code and I can't easily modify.
I'm running GHDL 3.0.0-dev (2.0.0.r689.gff1ef30e8) [Dunoon edition], set for VHDL-2008)