The documentation of GHDL contains a brief Quick Start Guide to introduce GHDL's CLI interface to users, but it does not contain an introduction to VHDL. There are many examples scattered in the repos:

• The testsuite of the main repo contains hundreds of reproducible examples. These are mostly undocumented, but most of them are small and are related to some public discussion.
• The examples and testsuite of ghdl-yosys-plugin contain tens of examples too. These use the plugin along with open source P&R and programming tools, such as nextpnr, icestorm, openocd, etc.
• Documented co-simulation examples about VPI and VHPIDIRECT are available in ghdl.github.io/ghdl-cosim.

However, since many users learn about both VHDL, GHDL and sometimes digital design at the same time, previous resources might be too harsh. The purpose of this document is to gather references to open/free (as in free beer) tutorials, guides, books, blog post, repositories, etc. which use VHDL (and optionally GHDL).

See also Talks, presentations and other communications about GHDL and Target projects for synthesis.

• IP databases and awesome lists:
  • opencores.org
  • librecores.org
  • hdl/awesome:
    • VHDL/awesome-vhdl
    • drom/awesome-hdl
    • fukatani/awesome-hdl
    • Vitorian/awesome-fpga
• VHDL Tutorial by Peter Ashenden (see Learning VHDL with GHDL #1291 (comment)).
• Book: VHDL Kompakt (German)
• Book: Free Range VHDL
• Book: datacipy.cz (Czech)
  • PDF, EPUB, MOBI
  • Materiály ke studiu a další
  • datacipy/VHDL
• nandland.com
  • VHDL Tutorials and Examples
• lauri.võsandi.com
  • Using GHDL to simulate VHDL
  • #GHDL
  • #VHDL
• dossmatik.de
  • dossmatik.de/vhdl
  • PDF: How to simulate an UART VHDL code with ghdl
  • PDF: GHDL simulate VHDL code with included Xilinx Library Unisim
• VHDL-2008: Why It Matters
• fpga4fun.com
• vhdlguide.com
  • Files – theory & examples
• vhdlwhiz.com: Basic VHDL Tutorials
• seas.upenn.edu/~ese171: VHDL Tutorial
• fpgatutorial.com/vhdl
• Rodrigo A. Melo:
  • Fundamentals of VHDL (Hardware Description Language) (slides, video)
  • FOSS (Free Open Source Software) for FPGA (slides, video)
  • VHDL for FPGA: Synthesis
  • VHDL for FPGA: Simulation
• Hipólito Guzmán:
  • sepagierm/sepa-practicas
  • edcmit/edc-practicas
• dev.to/targeted
  • Learning FPGA programming, key points for a software developer (part 1, the time)
  • Learning FPGA programming, key points for a software developer (part 2, registered logic)
  • Learning FPGA programming, key points for a software developer (part 3, code patterns and inferred behavior)
• bor.gs/vhdl: Apostila Aleatória de VHDL e GHDL
• TPU/RPU Series
  • Domipheus/TPU
  • Domipheus/RPU
  • Domipheus/ArtyS7-RPU-SoC
• Functional and formal verification
  • zipcpu.com: An Introduction to Formal Methods
  • tmeissner/psl_with_ghdl: examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  • tmeissner/vhdl_verification: examples and design pattern for VHDL verification
  • tmeissner/formal_hw_verification: trying to verify Verilog/VHDL designs with formal methods and tools
• Co-simulation with foreign languages/tools
  • ghdl.github.io/ghdl-cosim
    • Previous work and future ideas
    • List of open PRs
  • Asynchronous remote simulation using GHDL
  • Yann Guidon / YGDES:
    • VHDL library for gate-level verification
    • micro HTTP server in C
  • Virtual development boards:
    • gitlab.ensta-bretagne.fr/bollenth/ghdl-vpi-virtual-board
    • dbhi/vboard
• Code coverage with gcov
  • Evaluating VHDL Code Coverage Using GHDL and gcov
    • github.com/devsaurus/devsaurus.github.io/tree/master/ghdl_gco
  • Measuring code coverage with GHDL
• GHDL and OpenLane
  • britovski/adder (translation of staydh/adder)
  • antonblanchard/microwatt-caravel

Moreover, the following repositories (in case insensitive alphabetical order) might be useful for searching solutions to common designs/problems:

• alvieboy/ZPUino-HDL
• antonblanchard/microwatt
• benreynwar/htfft
• brimdavis/fpga_stuff
• brimdavis/yard-1
  • https://github.com/brimdavis/yard-1/tree/master/hdl/cores/m_uart
  • https://github.com/brimdavis/yard-1/tree/master/hdl/common/debounce
  • https://groups.io/g/fpga-cpu/message/660
  • https://github.com/brimdavis/yard-1/tree/master/verify
• daveshah1/CSI2Rx
• emard/ulx3s-misc
• https://github.com/fabioperez/space-invaders-vhdl
• hdl4fpga/hdl4fpga
• howerj/forth-cpu
• kevinpt/vhdl-extras
• kost/ulx3s-ghdl-examples
• marph91/icestick-remote
• marph91/icestick-uart
• marph91/pico-png
• marph91/pocket-cnn
• marph91/yaaes
• mbrobbel/capi-streaming-framework
• MiSTer-devel (?VHDL)
• MJoergen/nexys4ddr
• nkyparissas/Cellular_Automata_FPGA
• oetr/FPGA-I2C-Minion
• OSVVM/OSVVM
• Paebbels/JSON-for-VHDL
• Paebbels/PicoBlaze-Examples
• Paebbels/PicoBlaze-Library
• skordal/potato
• stnolting/neorv32
• suoto/fpga_cores
• tmeissner/cryptocores
• tmeissner/libvhdl
• VHDL/PoC
• VUnit/vunit
• XarkLabs/BenEaterVHDL
• xesscorp/VHDL_Lib
• xupgit/VHDL
• yol/ethernet_mac