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I hate two factor
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I hate two factor

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@asicguy
Frank Bruno asicguy
FPGA Architect/ Design engineer with 30 years experience. Worked for SpaceX, Allston Trading and Number Nine.

Naperville, IL

@tmeissner
T. Meissner tmeissner
FPGA-Engineer doing design and verification using VHDL, SystemVerilog, SVA and PSL.

Dresden, Germany

@Paebbels
Patrick Lehmann Paebbels
Vice-Chair of the IEEE P1076 Working Group (VHDL Analysis and Standardization Group- VASG). I'm a VHDL expert and FPGA-technology trainer at @PLC2.

@PLC2 Bötzingen, Germany

@JimLewis
Jim Lewis JimLewis
VHDL Verification Specialist, OSVVM author, VHDL Trainer (including on OSVVM), IEEE VHDL WG Chair, Yoga Teacher

SynthWorks / OSVVM Tigard, OR

@ATaylorCEngFIET
Adam Taylor ATaylorCEngFIET
Adam Taylor is an expert in design and development of embedded systems and FPGA's for several end applications.

http://adiuvoengineering.com/ United Kingdom

@cbourke
Chris Bourke cbourke
BIO!

University of Nebraska - Lincoln Nebraska