Type of issue: bug report

It seems that the commit in which the legacy Chisel compatibility is removed breaks the compilation when trying to attach a simple AXI4 memory mapped register.

Please see а detailed description of this bug, and how to reproduce the error.

What is the current behavior?

The code fails to build when trying to attach AXI4 memory mapped registers.

What is the expected behavior?

The code builds and generates Verilog with attached AXI4 memory mapped registers.

The commits before work fine, while the ones starting with 9a2d27b crash.