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Failed to detect width of signal

Status: Open.

#2772 In chipsalliance/synlig;

· L3odr0id opened on Aug 2, 2025

Port is connected to constants: { $auto$hierarchy.cc:1462:execute$1 1'0 }

Status: Open.

#2771 In chipsalliance/synlig;

· L3odr0id opened on Jul 30, 2025

Need to fix the way include hierarchy is parsed

Status: Open.

#2770 In chipsalliance/synlig;

· WrathofBhuvan11 opened on Jul 29, 2025

Break doesn't compile within a case

Status: Open.

#2769 In chipsalliance/synlig;

· mphipps1 opened on Jul 17, 2025

How do I build in debug mode?

Status: Open.

#2768 In chipsalliance/synlig;

· Rodrigodd opened on Jul 9, 2025

How to define a DEFINE is not documented

Status: Open.

#2710 In chipsalliance/synlig;

· rodrigomelo9 opened on Dec 18, 2024

Assignment inside for loop causes SEGV

Status: Open.

#2692 In chipsalliance/synlig;

· matsud224 opened on Dec 4, 2024

Segfault with certain typedef names

Status: Open.

#2647 In chipsalliance/synlig;

· s-holst opened on Nov 12, 2024

Invalid counter synthesis

Status: Open.

#2624 In chipsalliance/synlig;

· RustamC opened on Oct 22, 2024

casting to a vector of a given width not working properly

bugSomething isn't workingSomething isn't working

Status: Open.

#2618 In chipsalliance/synlig;

· jeras opened on Oct 17, 2024

Synlig has a problem with nested if else

Status: Open.

#2505 In chipsalliance/synlig;

· Kreijstal opened on Aug 4, 2024

Synthesis fail for opl3 example

Status: Open.

#2433 In chipsalliance/synlig;

· tarik-hamedovic opened on May 23, 2024