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@kammoh kammoh commented Apr 30, 2025

  • Adds the following options for generating traces using the Verilator backend:
    • maxArraySize: Maximum array depth for tracing
    • maxWidth: Maximum bit width for tracing
    • traceDepth: Depth of tracing

The corresponding Verilator flags are only added if the above integer values are > 0.

  • Adds TraceStyle.Fst for generating FST traces.

  • Removes the unused filename field from TraceStyle, which seemed very confusing. The trace file name (stem) is only configured through CommonSimulationSettings.traceFileStem.

I guess, technically an API change due to the change of the TraceStyle.Vcd case class?

Replaces #4910

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  • Feature (or new API)
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kammoh commented Apr 30, 2025

One question is if the default values for maxArraySize and maxWidth should be non-zero. Not being able to see arrays or wide signals in the waveform could be confusing to new-commers (or people less familiar with Verilator). I don't think performance is major concern as waveforms are only used for debugging, and from my experience any extra overhead is unnoticable. If the answer is yes, what choice values sounds reasonable?

@kammoh kammoh force-pushed the verilator_trace_options branch from 7c87e1c to 558a2bd Compare May 1, 2025 16:49
@kammoh kammoh requested a review from jackkoenig May 1, 2025 17:01
@seldridge seldridge added the Feature New feature, will be included in release notes label May 2, 2025
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This generally seems great to me. I have some nits about how to structure the options for Verilator to be more flexible.

@kammoh kammoh force-pushed the verilator_trace_options branch from 558a2bd to f6b4655 Compare May 21, 2025 22:45
@kammoh kammoh requested a review from seldridge May 22, 2025 00:03
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LGTM modulo nits.

@kammoh kammoh force-pushed the verilator_trace_options branch from 78f20bf to f67b3c2 Compare May 23, 2025 16:18
@jackkoenig jackkoenig merged commit d6da965 into chipsalliance:main May 24, 2025
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3 participants