[svsim] Add 'additionalArguments' to allow adding arbitrary flags to the Verilator backend #4910
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This allows adding arbitrary flags to the executed verilator command.
An example use case for me was adding "--trace-max-array" to be able to trace arrays in the generated waveforms.
Exposing all verilator flag in
CompilationSettings
seems impossible so this could be a way to allow for different use cases without cluttering up the Chisel side.Contributor Checklist
docs/src
?Type of Improvement
Desired Merge Strategy
Release Notes
Reviewer Checklist (only modified by reviewer)
3.6.x
,5.x
, or6.x
depending on impact, API modification or big change:7.0
)?Enable auto-merge (squash)
and clean up the commit message.Create a merge commit
.