Add the ability to better control the frequency of a simulation in
ChiselSim stimulus. Previously, this was left up to the simulator to
define and could result in some weird behaviors: Verilator defaults to
1ps/1ps (which would cause simulations to seemingly simulate very fast)
and VCS defaults to 1s/1s (which would cause simulations to seemingly
simulate very slowly).

Change the default behavior to simulate at 1GHz (by using a default
timescale of 1ns/100ps and making the clock period 10 precision units).
Additionally, make the first two steps of the reset procedure longer to
keep things nicely aligned in waveforms.

Due to how Verilator and non-Verilator (e.g., VCS) simulators are handled
differently by svsim, this requires some changes to align the two
implementations of the run_simulation function. For Verilator, this is
implemented in C++ and calls Verilator's timeInc(Int) function. This
will increment time by the precision. E.g., if the timescale is
1ns/100ps, then #2 will increment by 200ps. For non-Verilator, this
function is implemented in Verilog. Add an argument to an svsim function
that generates this Verilog to increment in multiples of precision.

After this PR, Verilator and VCS will generate the same VCD (checked by
inspection in a waveform).

Note 1: the change to run_simulation in Verilog is much easier in
1800-2023 as this has $timeunit and $timeprecision system functions.
However, VCS only supports 1800-2012.

Note 2: this is being done because some gate-level sims are being done
using ChiselSim and accurate power requires realistic frequencies. If
users don't care about this (or aren't integrating "real" models of
hardware) then this change shouldn't matter or affect users other than
seeing the units in the favorite waveform viewer change.

Here is the waveform I was inspecting: