[svsim][chiselsim] Add plusarg support #4796
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jackkoenig
approved these changes
Mar 15, 2025
Add the ability to pass plusargs to svsim simulations. Note: there is some ugliness here in that simulation options are passed to functions that are doing "compilation". This is a software architecture problem in svsim as evidenced by backend compilation options including runtime options (for VCS). This all needs to be cleaned up separately. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Add the ability to set `$value$plusarg` and `$test$plusargs` directly from ChiselSim simulate APIs. These can be specified using the lower level options to the simulator or via the implicit common/backend-specific options. However, this new API is the intended way that these should be set by the user going forward. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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Add the ability to set
$value$plusargand$test$plusargsdirectly fromChiselSim simulate APIs. These can be specified using the lower level
options to the simulator or via the implicit common/backend-specific
options. However, this new API is the intended way that these should be
set by the user going forward.
Add the ability to pass plusargs to svsim simulations.
Note: there is some ugliness here in that simulation options are passed to functions that are doing "compilation". This is a software architecture problem in svsim as evidenced by backend compilation options including runtime options (for VCS). This all needs to be cleaned up separately.
Release Notes
Add support for Verilog
$value$plusargsand$test$plusargsto svsim and ChiselSim.