[svsim] Error if waves enabled in unsupported sim #4787
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Neat! |
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Error, in Verilog, if an svsim simulator tries to enable waves in a simulation that wasn't compiled to support it. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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I included a test, but only for Verilator. I was not able to make this work cleanly for both Verilator and VCS testing due to the architecture of |
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Error, in Verilog, if an svsim simulator tries to enable waves in a simulation that wasn't compiled to support it.
Release Notes
Change svsim to error if a controller tries to enable waves in a simulation which wasn't compiled to support them.