[chiselsim] Add ControlAPI w/ Waveform Enable/Disable Support #4779
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Add a missing ChiselSim ControlAPI. This currently only includes APIs to enable and disalbe waveforms. This API was previously inaccessible because you would need to get at an svsim Controller to use it. Note: the enable/disable waveform APIs will have no effect unless the simulator is compiled with waveform support. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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| def enableWaves(): Unit = { | ||
| AnySimulatedModule.current.controller.setTraceEnabled(true) | ||
| } |
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Is it possible for this to error if the simulator was not compiled with waveform dumping?
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Frustratingly, I didn't see a clean way of doing this. I plan to come back and do this as part of svsim cleanup.
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I have a pure-Verilog solution to do this here: #4787
This produces output like:
# ./mill 'chisel[2.13.16].test.testOnly' 'chiselTests.simulator.scalatest.FooSpec' -- -z "terminate before 11 cycles"
[358/365] chisel[2.13.16].test.compile
[358] [info] compiling 1 Scala source to /Users/schuylereldridge/repos/github.com/chipsalliance/chisel/out/chisel/2.13.16/test/compile.dest/classes ...
[358] [info] done compiling
[365/365] chisel[2.13.16].test.testOnly
[365] FooSpec:
[365] Foo
[365] Bar
[365] - should terminate before 11 cycles have elapsed *** FAILED ***
[365] chisel3.simulator.Exceptions$AssertionFailed: One or more assertions failed during Chiselsim simulation
[365] ------------------------------------------------------------------------------
[365] The following assertion failures were extracted from the log file:
[365]
[365] lineNo line
[365] ----------------------------------------------------------------------------
[365] 0 [4] %Error: testbench.sv:97: Assertion failed in TOP.svsimTestbench.simulation_enableTrace: Cannot enable waves as this simulator was not compiled to support them
[365]
[365] For more information, see the complete log file:
[365]
[365] build/chiselsim/FooSpec/Bar/should-terminate-before-11-cycles-have-elapsed/workdir-verilator/simulation-log.txt
[365] ------------------------------------------------------------------------------
[365] ...
[365] Run completed in 1 second, 970 milliseconds.
[365] Total number of tests run: 1
[365] Suites: completed 1, aborted 0
[365] Tests: succeeded 0, failed 1, canceled 0, ignored 0, pending 0
[365] *** 1 TEST FAILED ***
[365/365] ======================= chisel[2.13.16].test.testOnly chiselTests.simulator.scalatest.FooSpec -- -z terminate before 11 cycles ====================== 4s
1 tasks failed
chisel[2.13.16].test.testOnly 1 tests failed:
chiselTests.simulator.scalatest.FooSpec Bar should terminate before 11 cycles have elapsed
|
Excited to see these improvements finally landing on svsim 🎉 |
I'm trying to figure out the right way to expose this via So, the way to do this today is to use simulateRaw(new Foo) { case dut =>
enableWaves()
ResetProcedure.module()(dut) // Or ResetProcedure.any if you don't have a Module
// user stimulus
}I'm considering adding an argument like |
Add a missing ChiselSim ControlAPI. This currently only includes APIs to
enable and disalbe waveforms. This API was previously inaccessible
because you would need to get at an svsim Controller to use it.
Note: the enable/disable waveform APIs will have no effect unless the
simulator is compiled with waveform support.
Release Notes
Add
ControlAPIto ChiselSim. This addsenableWavesanddisableWavesfunctions. These functions require compiling a simulator with waveform support.