This also needs to remap layer colored probes.

This should also probably grow a feature for remapping to the root layer with the effect. This has overlap with CIRCT specialization flows, but is necessary in order to produce legal FIRRTL.

Should this feature goes to circt by adding some cmdline option?

another idea is we can simply append the package name of each layer to identify them(or provide an user defined override-able val instead.)

Should this feature goes to circt by adding some cmdline option?

A variation of this will need to show up as a FIRRTL language feature. However, I don't want to have CIRCT handle corrections to illegal FIRRTL to make it legal. I want to have Chisel always be able to emit legal FIRRTL.

E.g., we need some kind of "layer alias" or "layer remapping" at an extmodule boundary:

circuit Foo:
  layer A:
  extmodule Bar:
    layer B as A:
  module Foo:
    inst bar of Bar    

In the above Bar was compiled to Verilog with a layer Bar::B. (Which means it has a bunch of optional functionality that can be enabled by including a file layers_Bar_B.sv in the compilation). From the FIRRTL side, we need to know how to enable layer B in relation to the existing layers that Foo has. The above would cause layers A and Bar::B to be enabled at the same time and allow for any intermixing of layer colors A and Bar::B`

another idea is we can simply append the package name of each layer to identify them(or provide an user defined override-able val instead.)

I wanted a more Chisel language level way of doing this but couldn't come up with something. The problem is that there is no "global configuration" for Chisel where you can do this. Where could you put a val that would set this globally? It could be an implicit that is passed everywhere. However, that implicit has the possibility of being overridden and for you to get legal FIRRTL out of Chisel it can't be overridden. There's similar problems with things like withLayer[A](thunk: => A) which can be overridden by some upstream library.

All that said, practically, I don't think that this feature will be frequently used. I want most people to align on the upstream provided layers that Chisel has. Draft PR here: https://github.com/chipsalliance/chisel/pull/4323/files#diff-ef2aee2c3e90ffd56af995e76ac6573da3db4f939ea66b5c2f95756c29041504 These then give us a common place to put assertions for standard library generators or internal things. Users are then free to add more layers based on what they care about. (There is a missing feature to add a layer that is a parent of an existing layer.)

This also needs to remap layer colored probes.

Added in: fdfdff9