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	modified:   src/main/scala/chisel3/util/SRAM.scala

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Original PR Body

It is sometimes desirable to instantiate a memory with ports clocked with different clocks (e.g. clock domain crossing). This PR adds additional APIs to SRAM which allow users to drive ports using a sequence of clocks:

// Create a multi-clocked 3R, 2W SRAM
val mem = SRAM(
  1024, 
  UInt(8.W), 
  Seq(clock1, clock2, clock3), // Memory read port clocks
  Seq(clock4, clock5),         // Memory write port clocks
  Seq.empty                    // Memory read-write port clocks
)

Contributor Checklist

• Did you add Scaladoc to every public function/method?
• Did you add at least one test demonstrating the PR?
• Did you delete any extraneous printlns/debugging code?
• Did you specify the type of improvement?
• Did you add appropriate documentation in docs/src?
• Did you request a desired merge strategy?
• Did you add text to be included in the Release Notes for this change?

Type of Improvement

• Feature (or new API)

Desired Merge Strategy

Squash

Release Notes

Add new SRAM APIs that take three Clock sequences as parameters instead of the number of read/write/read-write ports. This will sequentially instantiate a memory port for each clock in the Clock sequence and drive them accordingly.

Reviewer Checklist (only modified by reviewer)

• Did you add the appropriate labels? (Select the most appropriate one based on the "Type of Improvement")
• Did you mark the proper milestone (Bug fix: 3.5.x or 3.6.x depending on impact, API modification or big change: 5.0.0)?
• Did you review?
• Did you check whether all relevant Contributor checkboxes have been checked?
• Did you do one of the following when ready to merge:
  • Squash: You/ the contributor Enable auto-merge (squash), clean up the commit message, and label with Please Merge.
  • Merge: Ensure that contributor has cleaned up their commit history, then merge with Create a merge commit.