Add generator APIs for constructing memories with an exact number of read, write, and readwrite ports. This enables designers to avoid odd behavioral rules and makes the Verilog generated match their intent.

For now, this can be a wrapper around a module (or just a class) that will use the existing memory inference rules so that it will produce the desired output. In the future this can be changed to directly building a FIRRTL memory or using a memory intrinsic.