If you bitselect incorrectly, like from low to high instead of high to low, you get this unhelpful requirement failure:

[error] Exception in thread "main" java.lang.IllegalArgumentException: requirement failed
[error]         at scala.Predef$.require(Predef.scala:264)
[error]         at chisel3.internal.firrtl.KnownWidth.<init>(IR.scala:202)
[error]         at chisel3.internal.firrtl.Width$.apply(IR.scala:176)
[error]         at chisel3.core.Bits.$anonfun$do_apply$6(Bits.scala:221)
[error]         at scala.Option.getOrElse(Option.scala:121)
[error]         at chisel3.core.Bits.do_apply(Bits.scala:219)

This is caused by Chisel trying to create a negative width UInt. Now this error does have a better message (https://github.com/freechipsproject/chisel3/blob/a4a29e29c3f1eed18f851dcf10bdc845571dfcb6/chiselFrontend/src/main/scala/chisel3/core/Bits.scala#L160), but it uses Builder.error which doesn't get reported if a later exception occurs. We can obviously patch this specific issue, but I wonder if better handling of such cases in general would be a better solution.

Type of issue: bug report

Impact: no functional change

Development Phase: request
Other information

If the current behavior is a bug, please provide the steps to reproduce the problem:

import chisel3._

class MyModule extends Module {
  val io = IO(new Bundle {
    val in = Input(UInt(8.W))
    val out = Output(UInt())
  })
  
  io.out := io.in(0, 3)
} 

object MyMain extends App {
  println(chisel3.Driver.emitVerilog(new MyModule))
} 

What is the current behavior?

See above

What is the expected behavior?

See above

What is the use case for changing the behavior?

Better user experience