//> using scala "2.13.12"
//> using dep "org.chipsalliance::chisel:6.4.0"
//> using plugin "org.chipsalliance:::chisel-plugin:6.4.0"
//> using options "-unchecked", "-deprecation", "-language:reflectiveCalls", "-feature", "-Xcheckinit", "-Xfatal-warnings", "-Ywarn-dead-code", "-Ywarn-unused", "-Ymacro-annotations"

import chisel3._
import chisel3.reflect.DataMirror
// _root_ disambiguates from package chisel3.util.circt if user imports chisel3.util._
import _root_.circt.stage.ChiselStage

class MyBundle extends Bundle {
  val a = Output(UInt(8.W))
  val b = UInt(8.W)
}

class Foo extends Module {

  val w = Wire(new MyBundle)

  println(DataMirror.directionOf(w))
}

object Main extends App {
  ChiselStage.emitCHIRRTL(new Foo)
}