//> using scala "2.13.12"
//> using dep "org.chipsalliance::chisel:6.3.0"
//> using plugin "org.chipsalliance:::chisel-plugin:6.3.0"
//> using options "-unchecked", "-deprecation", "-language:reflectiveCalls", "-feature", "-Xcheckinit", "-Xfatal-warnings", "-Ywarn-dead-code", "-Ywarn-unused", "-Ymacro-annotations"

import chisel3._
import chisel3.simulator.EphemeralSimulator._
// _root_ disambiguates from package chisel3.util.circt if user imports chisel3.util._
import _root_.circt.stage.ChiselStage

class Foo extends Module {
  val io = FlatIO(new Bundle {
    val in = Input(UInt(8.W))
    val out = Output(UInt(8.W))
  })

  val delay = RegNext(io.in)
  io.out := delay
}

object Main extends App {
  println(
    ChiselStage.emitSystemVerilog(
      gen = new Foo,
      firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info")
    )
  )
  simulate(new Foo) { c =>
    c.io.in.poke(12.U)
    c.clock.step()
    c.io.out.peek()
  }
}