Also bump softprops/action-gh-release to v2.1.0.

(cherry picked from commit 25d00af)

Co-authored-by: Jack Koenig <koenig@sifive.com>

(cherry picked from commit 4177bfa)

Co-authored-by: qiming chu <cchuqiming@gmail.com>

When added require statement in ChiselSim/svsim, the delay value will be
set to 0, which will cause an extra dump waveform behavior. So we only
call `eval_step` once to update the design model

(cherry picked from commit 3380196)

Co-authored-by: qiming chu <cchuqiming@gmail.com>

…4606)

(cherry picked from commit d4d3e97)

Co-authored-by: Jason Wang <174672328+AptInit@users.noreply.github.com>

* save the elementContainsProbes for an Aggregate to speed up various computations
* add unit tests for ContainsProbe

(cherry picked from commit c9cecfa)

Co-authored-by: Megan Wachs <megan@sifive.com>

(cherry picked from commit 63b129d)

Co-authored-by: Jerry Zhao <jerryz123@berkeley.edu>

…ort #4683) (#4693)

* Add ElaboratedCircuit and deprecate use of internal ir Circuit (#4683)

Change ChiselCircuitAnnotation and CircuitSerializationAnnotation to no
longer be case classes to help with the transition to ElaboratedCircuit.

(cherry picked from commit 4d75573)

# Conflicts:
#	core/src/main/scala/chisel3/experimental/hierarchy/core/Definition.scala
#	core/src/main/scala/chisel3/internal/Builder.scala
#	src/main/scala/chisel3/stage/ChiselOptions.scala
#	src/main/scala/chisel3/stage/phases/AddImplicitOutputAnnotationFile.scala
#	src/main/scala/chisel3/stage/phases/AddImplicitOutputFile.scala
#	src/main/scala/chisel3/stage/phases/Convert.scala
#	src/main/scala/chisel3/stage/phases/Elaborate.scala
#	src/test/scala/circtTests/stage/ChiselStageSpec.scala

* Resolve backport conflicts

* MiMa waive package private constructor change

* Fix ScalaDoc

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

…4697)

* Add safer Chisel annotation API, deprecate old ones (#4643)

The new one enables safety checks and smarter logic for views.

(cherry picked from commit a95cfe4)

# Conflicts:
#	build.mill
#	build.sbt
#	core/src/main/scala/chisel3/Annotation.scala
#	core/src/main/scala/chisel3/ChiselEnum.scala
#	core/src/main/scala/chisel3/Module.scala
#	core/src/main/scala/chisel3/dontTouch.scala
#	core/src/main/scala/chisel3/experimental/hierarchy/core/Definition.scala
#	src/main/scala/chisel3/util/AttributeAnnotation.scala
#	src/main/scala/chisel3/util/experimental/Inline.scala
#	src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala
#	src/main/scala/circt/OutputDirAnnotation.scala
#	src/test/scala-2/chiselTests/util/SRAMSpec.scala
#	src/test/scala/chiselTests/AnnotatingDiamondSpec.scala
#	src/test/scala/chiselTests/experimental/hierarchy/Annotations.scala
#	src/test/scala/circtTests/stage/ChiselStageSpec.scala

* Resolve backport conflicts

* Waive false MiMa issues

* Fix ScalaDoc

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>

…4743)

* [testers] Deprecate everything the testers package (#4742)

Deprecate `BasicTester` and `TesterDriver`.  These have been fully
replaced with ChiselSim.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
(cherry picked from commit 0a0fa80)

# Conflicts:
#	src/test/scala/chiselTests/TesterDriverSpec.scala

* fixup! [testers] Deprecate everything the testers package (#4742)

* fixup! [testers] Deprecate everything the testers package (#4742)

---------

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* Mass deprecations, to be removed in Chisel 7 (#4754)

Mass deprecation of APIs that we would like to delete in Chisel 7.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com
(cherry picked from commit 868c195)

# Conflicts:
#	firrtl/src/test/scala/firrtlTests/FileUtilsSpec.scala
#	src/test/scala/chiselTests/Harness.scala

* fixup! Mass deprecations, to be removed in Chisel 7 (#4754)

* fixup! Mass deprecations, to be removed in Chisel 7 (#4754)

---------

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* Refine annotate and Targetable (#4698)

Some minor improvements to the user API for annotating with Targetable
* Support annotating Seq[Targetable] and provide Targetable for AnyTargetable.
* Add AnyTargetable.apply for simpler manual conversions.
* Show tests annotating Seq[Targetable] and manual use of AnyTargetable.

(cherry picked from commit e20069e)

* Run formatting

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>

The user probably forgot .W. Apply the same technique as used for .U|.S.

(cherry picked from commit 811bb46)

Co-authored-by: Jack Koenig <koenig@sifive.com>

#4565)

* Escape special characters in Property String literals (#4564)

(cherry picked from commit dc39308)

* Tweak change to make it binary compatible

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Fix ModuleChoice under D/I (#4569)

* Use FileCheck in ModuleChoice tests; add a test
* DRY out module definitions in ModuleChoiceSpec
* Add a ModuleChoice test using Definition
* Ensure Groups are propagated to parent builder under D/I

(cherry picked from commit 0070570)

# Conflicts:
#	core/src/main/scala/chisel3/experimental/hierarchy/core/Definition.scala

* Resolve backport conflicts

* Tweak tests back to 6.x-style

---------

Co-authored-by: David Biancolin <david.biancolin@gmail.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

) (#4604)

* Support boring on original Module after .toInstance call (#4602)

(cherry picked from commit 4d162c4)

* Add needed private API and change new test to 6.x-style

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>