ARM64_REG_Vx vs. ARM64_REG_Qx #2363
Description
For instruction mov w20, v1.s[0] (0x0e043c34),
I get the correct information with the version 5.0.0:
# cstool -d arm64be 0e043c34
0 0e 04 3c 34 mov w20, v1.s[0]
ID: 488 (mov)
op_count: 2
operands[0].type: REG = w20
operands[0].access: WRITE
operands[1].type: REG = v1
operands[1].access: READ
Vector Arrangement Specifier: 0xb
Vector Index: 0
Registers read: v1
Registers modified: w20
Groups: neon
Whereas, with the next branch, I get q1 instead of v1 for the second operand:
# ./cstool/cstool -d aarch64be 0e043c34
0 0e 04 3c 34 mov w20, v1.s[0]
ID: 1232 (umov)
Is alias: 1349 (mov) with ALIAS operand set
op_count: 2
operands[0].type: REG = w20
operands[0].access: WRITE
operands[1].type: REG = q1
operands[1].access: READ
Vector Arrangement Specifier: 0x20
Vector Index: 0
Registers read: q1
Registers modified: w20
Groups: HasNEONorSME
Although the names v1 and q1 refer to the same register, their interpretations are different (i.e., q1 as a single 128-bit quantity while v0 as a vector of something).